# US 12,183,806 B2 · Semiconductor devices and methods of fabricating the same

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- Number: US 12,183,806 B2
- Document ID: US12183806B2
- Status: Granted
- Kind: B2
- Application number: 17/732,140
- Filed: 2022-04-28
- Published: 2023-11-02
- Granted: 2024-12-31
- Earliest claimed: 2022-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ko-Cheng Liu; Chang-Miao Liu
- Web page: https://patentgrep.com/patent/US12183806B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0153: {using gate cut processes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes providing a workpiece having a first active region and a second active region protruding from a substrate, lined by cladding layers, and spaced by a first trench. The method also includes forming a dielectric layer over the workpiece to substantially fill the first trench, forming a mask film directly on a portion of the dielectric layer in the first trench after the forming of the dielectric layer, selectively recessing the dielectric layer after the forming of the mask film to form a dummy fin in and protruding from the first trench, performing an etching process to selectively remove the cladding layers to form second trenches, and forming a gate structure over the workpiece to fill the second trenches.

## Claims

### Claim 1

A method, comprising:
providing a workpiece comprising:
a first active region and a second active region protruding from a substrate and spaced by a first trench, and
cladding layers extending along sidewalls of the first active region and the second active region, wherein the cladding layers partially fill the first trench;
forming a dielectric layer over the workpiece to substantially fill the first trench;
after the forming of the dielectric layer, forming a mask film directly on a portion of the dielectric layer in the first trench;
after the forming of the mask film, selectively recessing the dielectric layer to form a dummy fin in and protruding from the first trench;
performing an etching process to selectively remove the cladding layers to form second trenches; and
forming a gate structure over the workpiece to fill the second trenches.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
after the forming of the gate structure, forming source/drain features over the workpiece; and
replacing the gate structure with a metal gate stack,
wherein a top surface of the dummy fin is above a top surface of the metal gate stack.

### Claim 3 (depends on 2)

The method of claim 2, wherein the replacing the gate structure with the metal gate stack comprises performing an etching process to selectively remove the gate structure without substantially etching the dummy fin.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
after the performing of the etching process, selectively removing the mask film; and
performing another etching process to trim a portion of the dummy fin that protrudes from the first trench.

### Claim 5 (depends on 1)

The method of claim 1, wherein the etching process is performed after the forming of the dummy fin.

### Claim 6 (depends on 1)

The method of claim 1,
wherein the first active region and the second active region each includes a vertical stack of alternating channel layers and sacrificial layers, and
wherein the performing of the etching process removes the cladding layers while not substantially etching the channel layers and sacrificial layers.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
after the forming of the gate structure, recessing regions of the first active region and the second active region that are not covered by the gate structure to form source/drain trenches;
selectively recessing the sacrificial layers to form inner spacer recesses;
forming inner spacer features in the inner spacer recesses; and
forming source/drain features in the source/drain trenches.

### Claim 8 (depends on 1)

The method of claim 1, wherein the forming of the dielectric layer over the workpiece comprises:
forming a conformal dielectric liner over the workpiece to partially fill the first trench;
forming a first dielectric filler over the workpiece to substantially fill a bottom portion of the first trench; and
forming a second dielectric filler over the workpiece to substantially fill an upper portion of the first trench.

### Claim 9 (depends on 8)

The method of claim 8, wherein a composition of the second dielectric filler is the same as a composition of the conformal dielectric liner, and a composition of the first dielectric filler is different from a composition of the conformal dielectric liner.

### Claim 10

A method, comprising:
providing a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin each protruding from a substrate and oriented lengthwise in a first direction;
forming a dielectric feature over the substrate to fill space between the first and second semiconductor fins and space between the second and third semiconductor fins;
selectively recessing the dielectric feature to form a first isolation feature between the first and second semiconductor fins and a second isolation feature between the second and third semiconductor fins, wherein a height of the first isolation feature is greater than a height of the second isolation feature;
after the forming of the first and second isolation features, forming a placeholder gate over the first, second, and third semiconductor fins, wherein the first and the second isolation features are embedded in the placeholder gate;
forming source/drain features;
selectively removing the placeholder gate without substantially etching the first and second isolation features; and
forming a metal gate stack over the substrate, wherein a top surface of the first isolation feature is above a top surface of the metal gate stack, and a top surface of the second isolation feature is below a top surface of the metal gate stack.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
before the forming of the dielectric feature, forming cladding layers extending along sidewalls of the first, second, and third semiconductor fins; and
before the forming of the placeholder gate, selectively removing the cladding layers.

### Claim 12 (depends on 11)

The method of claim 11, wherein the cladding layers comprise aluminum oxide or silicon germanium.

### Claim 13 (depends on 12)

The method of claim 12, wherein a germanium concentration of the cladding layers is different than a germanium concentration of a semiconductor layer of the first, second, and third semiconductor fins.

### Claim 14 (depends on 10)

The method of claim 10, wherein the height of the second isolation feature is substantially equal to a height of the first, second, and third semiconductor fins.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
before the selectively recessing of the dielectric feature, forming a patterned mask film directly over a portion of the dielectric feature disposed between the first and second semiconductor fins; and
after the selectively recessing of the dielectric feature, selectively removing the patterned mask film.

### Claim 16 (depends on 10)

The method of claim 10, wherein the forming of the dielectric feature over the substrate comprises:
depositing a first dielectric layer over the substrate to fill bottom portions of the space between the first and second semiconductor fins and space between the second and third semiconductor fins; and
depositing a second dielectric layer over the substrate to fill upper portions of the space between the first and second semiconductor fins and space between the second and third semiconductor fins,
wherein the selectively recessing of the dielectric feature includes selectively recessing the second dielectric layer, and the selectively recessing of the dielectric feature stops before reaching a top surface of the first dielectric layer.

### Claim 17 (depends on 10)

The method of claim 10, wherein the first, second, and third semiconductor fins each includes a vertical stack of alternating first semiconductor layers and second semiconductor layers that are different from the first semiconductor layers.

### Claim 18

A semiconductor structure, comprising:
a first plurality of channel members over a substrate;
a second plurality of channel members over the substrate;
a third plurality of channel members over the substrate;
a gate structure wrapping around the first, second, and third plurality of channel members;
a first dummy fin disposed between the first plurality of channel members and the second plurality of channel members; and
a second dummy fin disposed between the second plurality of channel members and the third plurality of channel members,
wherein a top surface of the first dummy fin is above a top surface of the gate structure, and a top surface of the second dummy fin is below a top surface of the gate structure.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein the first dummy fin comprises silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbon oxynitride (SiOCN), silicon carbonitride (SiCN), hafnium oxide (HfO2), or aluminum oxide (Al2O3).

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein the first dummy fin comprises a first dielectric layer embedded in a second dielectric layer, and a dielectric constant of the second dielectric layer is different from a dielectric constant of the first dielectric layer.