# US 12,183,801 B2 · Semiconductor device and method for fabricating the same

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- Number: US 12,183,801 B2
- Document ID: US12183801B2
- Status: Granted
- Kind: B2
- Application number: 17/510,394
- Filed: 2021-10-26
- Published: 2023-03-30
- Granted: 2024-12-31
- Earliest claimed: 2021-09-27
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Jin-Yan Chiou; Wei-Chuan Tsai; Yen-Tsai Yi; Hsiang-Wen Ke
- Web page: https://patentgrep.com/patent/US12183801B2

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/033: {in openings in dielectrics}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate structure on a substrate;
a source/drain region adjacent to two sides of the gate structure;
a contact plug adjacent to the gate structure and on the source/drain region, wherein the contact plug comprises:
an epitaxial layer on the source/drain region;
an interface layer on the epitaxial layer, wherein the interface layer comprises silicon germanium;
a first silicide layer on the interface layer;
a second silicide layer on the first silicide layer, wherein both the first silicide layer and the second silicide layer comprise an I-shape;
a barrier layer on the second silicide layer; and
a conductive layer on the barrier layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of germanium in the interface layer is less than a concentration of germanium in the first silicide layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of germanium in the interface layer is less than a concentration of germanium in the epitaxial layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the barrier layer comprises titanium nitride (TiN).

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the conductive layer comprises tungsten (W).

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first silicide layer comprises a metal germanosilicide.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second silicide layer comprises a metal silicide.