# US 12,183,800 B2 · Semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,800 B2 - Document ID: US12183800B2 - Status: Granted - Kind: B2 - Application number: 18/449,734 - Filed: 2023-08-15 - Published: 2023-11-30 - Granted: 2024-12-31 - Earliest claimed: 2020-07-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Myung Gil Kang; Dong Won Kim; Woo Seok Park; Keun Hwi Cho; Sung Gi Hur - Web page: https://patentgrep.com/patent/US12183800B2 ## CPC - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 62/364: {of IGFETs} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0167: {Manufacturing their channels} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth. ## Claims ### Claim 1 A semiconductor device comprising: a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern, the first lower pattern including a first sidewall and a second sidewall opposite to each other; a second active pattern including a second lower pattern spaced apart from the first lower pattern in a second direction different from the first direction and a second sheet pattern spaced apart from the second lower pattern, the second lower pattern including a third sidewall facing the second sidewall and a fourth sidewall opposite to the third sidewall; a first gate electrode on the first lower pattern and the second lower pattern, the first gate electrode extending in the second direction and surrounding at least a portion of the first sheet pattern and a portion of the second sheet pattern; a first gate insulating layer extending along the first active pattern and the second active pattern, a first cell isolation structure facing the first sidewall; and a second cell isolation structure facing the fourth sidewall, wherein a first width of the first gate electrode between the second sidewall and the third sidewall is greater than a second width of the first gate electrode between the first cell isolation structure and the first sidewall, wherein the second width of the first gate electrode is greater than a third width of the first gate electrode between the fourth sidewall and the second cell isolation structure, wherein the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, the first gate electrode overlaps the third sidewall of the second lower pattern in the second direction by a third depth, the first gate electrode overlaps the fourth sidewall of the second lower pattern in the second direction by a fourth depth, and the second depth is equal to the third depth and is greater than the first depth, the third depth is greater than the fourth depth, the first depth is greater than the fourth depth, and wherein a bottom surface of the first cell isolation structure is lower than a lowermost surface of the first gate insulating layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein: a width of a top surface of the first lower pattern and a width of a top surface of the second lower pattern are equal. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first gate insulating layer extends along a sidewall of the first cell isolation structure and a sidewall of the second cell isolation structure. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein: a width of the first cell isolation structure and a width of the second cell isolation structure are equal. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein: a width of the first sheet pattern decreases as a distance from the first lower pattern increases. ### Claim 6 A semiconductor device comprising: a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern, the first lower pattern including a first sidewall and a second sidewall opposite to each other; a second active pattern including a second lower pattern spaced apart from the first lower pattern in a second direction different from the first direction and a second sheet pattern spaced apart from the second lower pattern, the second lower pattern including a third sidewall facing the second sidewall and a fourth sidewall opposite to the third sidewall; a third active pattern including a third lower pattern spaced apart from the first lower pattern in the second direction and a third sheet pattern spaced apart from the third lower pattern, the third lower pattern including a fifth sidewall facing the fourth sidewall and a sixth sidewall opposite to the fifth sidewall; and a first gate electrode on the first lower pattern, the second lower pattern and the third lower pattern, the first gate electrode extending in the second direction and surrounding at least a portion of the first sheet pattern, a portion of the second sheet pattern and a portion of the third sheet pattern, wherein the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the fourth sidewall of the second lower pattern in the second direction by a second depth, wherein the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a third depth, the first depth is less than the second depth, and the third depth is less than the second depth. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein a first distance between the second sidewall and the third sidewall is less than a second distance between the fourth sidewall and the fifth sidewall. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the first gate electrode overlaps the fifth sidewall of the second lower pattern in the second direction by a fourth depth, and the second depth and the fourth depth are equal. ### Claim 9 (depends on 6) The semiconductor device of claim 6, wherein the third depth is greater than the first depth. ### Claim 10 (depends on 6) The semiconductor device of claim 6, wherein a width of a top surface of the first lower pattern and a width of a top surface of the second lower pattern are equal. ### Claim 11 (depends on 6) The semiconductor device of claim 6, wherein a width of a top surface of the first lower pattern and a width of a top surface of the second lower pattern are less than a width of a top surface of the third lower pattern. ### Claim 12 (depends on 6) The semiconductor device of claim 6, further comprising: a first cell isolation structure facing the first sidewall and intersecting the first gate electrode; and a second cell isolation structure facing the sixth sidewall and intersecting the first gate electrode, wherein a third distance between the first cell isolation structure and the first sidewall and a fourth distance between the second cell isolation structure and the sixth sidewall are less than a fifth distance between the fourth sidewall and the fifth sidewall. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a width of the first cell isolation structure and a width of the second cell isolation structure are equal. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein a distance between the first cell isolation structure and the first sidewall is greater than a distance between the second sidewall and the third sidewall. ### Claim 15 (depends on 6) The semiconductor device of claim 6, wherein the first gate electrode overlaps the fifth sidewall of the second lower pattern in the second direction by a fourth depth, the first gate electrode overlaps the sixth sidewall of the second lower pattern in the second direction by a fifth depth, and the fifth depth is less than the fourth depth. ### Claim 16 A semiconductor device comprising a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern, the first lower pattern including a first sidewall and a second sidewall opposite to each other; a second active pattern including a second lower pattern spaced apart from the first lower pattern in a second direction different from the first direction and a second sheet pattern spaced apart from the second lower pattern, the second lower pattern including a third sidewall facing the second sidewall and a fourth sidewall opposite to the third sidewall; a first gate electrode on the first lower pattern and the second lower pattern, the first gate electrode extending in the second direction and surrounding at least a portion of the first sheet pattern and a portion of the second sheet pattern; a first cell isolation structure facing the first sidewall; and a second cell isolation structure facing the fourth sidewall, wherein the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, the first gate electrode overlaps the third sidewall of the second lower pattern in the second direction by a third depth, the first gate electrode overlaps the fourth sidewall of the second lower pattern in the second direction by a fourth depth, the fourth depth is less than the third depth, and the first depth is less than the second depth. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein: a first distance between the first cell isolation structure and the first sidewall and a second distance between the second cell isolation structure and the fourth sidewall are less than a third distance between the second sidewall and the third sidewall. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein: the second depth and the third depth are equal. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein: a width of a top surface of the first lower pattern and a width of a top surface of the second lower pattern are equal. ### Claim 20 (depends on 16) The semiconductor device of claim 16, wherein: the first depth and the fourth depth are equal.