# US 12,183,799 B2 · Semiconductor device with gate isolation features and fabrication method of the same

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- Number: US 12,183,799 B2
- Document ID: US12183799B2
- Status: Granted
- Kind: B2
- Application number: 18/447,870
- Filed: 2023-08-10
- Published: 2023-12-07
- Granted: 2024-12-31
- Earliest claimed: 2021-03-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jung-Chien Cheng; Kuo-Cheng Chiang; Shi Ning Ju; Guan-Lin Chen; Jia-Chuan You; Chia-Hao Chang; Chih-Hao Wang; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US12183799B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures. The first isolation feature is in physical contact with the first and second gate structures.

## Claims

### Claim 1

A semiconductor device, comprising:
a first channel member over a first backside dielectric feature;
a first gate structure engaging the first channel member;
a second channel member over a second backside dielectric feature;
a second gate structure engaging the second channel member; and
a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures, wherein the first isolation feature is in physical contact with the first and second gate structures.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second portion has a larger width than the first portion.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each of the first and second gate structures includes a gate dielectric layer and a gate electrode layer, and wherein the second portion of the first isolation feature is in physical contact with the gate electrode layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the first isolation feature is substantially coplanar with a top surface of the first and second gate structures.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second isolation feature disposed on a top surface of the first isolation feature, wherein a top surface of the second isolation feature is above a top surface of the first and second gate structures.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a metal capping layer disposed on the top surface of the first and second gate structures, wherein the second isolation feature divides the metal capping layer into two segments.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the second portion has a larger width than the second isolation feature.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first spacer disposed between the first backside dielectric feature and the first portion; and
a second spacer disposed between the second backside dielectric feature and the first portion.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first gate structure wraps around the first channel member, and the second gate structure wraps around the second channel member.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first epitaxial feature abutting the first channel member; and
a second epitaxial feature abutting the second channel member,
wherein the first isolation feature includes a third portion laterally between the first and second epitaxial features.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second portion has a larger width than the third portion.

### Claim 12

A semiconductor device, comprising:
a plurality of channel members over a backside dielectric feature;
a gate structure wrapping around each of the channel members;
a first isolation feature disposed on a first sidewall of the gate structure, the first isolation feature extending vertically from a bottom surface of the backside dielectric feature to a top surface of the gate structure; and
a second isolation feature disposed on a second sidewall of the gate structure, the second isolation feature extending vertically from the bottom surface of the backside dielectric feature to the top surface of the gate structure.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising:
a metal capping layer covering the top surface of the gate structure and covering a top surface of the first isolation feature.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising:
a third isolation feature disposed on a top surface of the second isolation feature, wherein a top surface of the third isolation feature is above a top surface of the metal capping layer.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, further comprising:
a gate contact landing on the metal capping layer.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein each of the first and second isolation features is in physical contact with a gate electrode layer of the gate structure.

### Claim 17

A semiconductor device, comprising:
a first plurality of channel members over a first backside dielectric feature;
a second plurality of channel members over a second backside dielectric feature;
a first source/drain feature abutting the first plurality of channel members and over the first backside dielectric feature;
a second source/drain feature abutting the second plurality of channel members and over the second backside dielectric feature;
a first gate structure wrapping around each of the first plurality of channel members;
a second gate structure wrapping around each of the second plurality of channel members;
a metal capping layer disposed on the first and second gate structures;
a first isolation feature includes a first portion stacked between the first and second gate structures and a second portion stacked between the first and second source/drain features; and
a second isolation feature through the metal capping layer and landing on the first isolation feature.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first portion of the first isolation feature has a width larger than the second portion of the first isolation feature.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the first isolation feature includes a third portion stacked between the first and second backside dielectric features, wherein the first portion of the first isolation feature has a width larger than the third portion of the first isolation feature.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, further comprising:
a first spacer stacked between the first backside dielectric feature and the first isolation feature; and
a second spacer stacked between the second backside dielectric feature and the first isolation feature.