# US 12,183,798 B2 · Threshold voltage modulation for gate-all-around FET architecture

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- Number: US 12,183,798 B2
- Document ID: US12183798B2
- Status: Granted
- Kind: B2
- Application number: 17/528,863
- Filed: 2021-11-17
- Published: 2022-07-28
- Granted: 2024-12-31
- Earliest claimed: 2021-01-25
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Steven C. H. Hung; Benjamin Colombeau; Myungsun Kim; Srinivas Gandikota; Yixiong Yang; Jacqueline Samantha Wrench; Yong Yang
- Web page: https://patentgrep.com/patent/US12183798B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 64/685: {being perpendicular to the channel plane}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

## Claims

### Claim 1

A method of forming a gate stack structure, the method comprising:
forming a dipole metal layer on a high-gate dielectric layer on a semiconductor structure formed on a substrate;
annealing the dipole metal layer; and
removing the dipole metal layer, wherein
the dipole metal layer comprises dopants in the high-K gate dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the dipole metal layer comprises:
blanket depositing the dipole metal layer on the semiconductor structure; and
patterning the dipole metal layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein
the high-K gate dielectric layer comprises hafnium oxide (HfO2).

### Claim 4 (depends on 3)

The method of claim 3, wherein
the dipole metal layer comprises lanthanum (La).

### Claim 5 (depends on 3)

The method of claim 3, wherein
the dipole metal layer comprises aluminum (Al).

### Claim 6 (depends on 3)

The method of claim 3, wherein
the dipole metal layer comprises niobium (Nb).

### Claim 7 (depends on 1)

The method of claim 1, wherein
the dipole metal layer has a thickness of between 3 Å and 20 Å.

### Claim 8

A method of forming a gate stack structure, the method comprising:
forming a p-type work function adjusting layer on a high-k gate dielectric layer on a semiconductor structure formed on a substrate;
forming an n-type work function adjusting layer on the high-K gate dielectric layer; and
forming a metal gate electrode on the p-type work function adjusting layer and the n-type work function adjusting layer, wherein
the p-type work function adjusting layer comprises p-doped conductive material, and
the n-type work function adjusting layer comprises n-doped conductive material.

### Claim 9 (depends on 8)

The method of claim 8, wherein
the metal gate electrode comprises tungsten (W).

### Claim 10 (depends on 8)

The method of claim 8, wherein
the p-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

### Claim 11 (depends on 8)

The method of claim 8, wherein
the n-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

### Claim 12

A method of forming a gate stack structure on a semiconductor structure, the method comprising:
forming an interfacial layer on a semiconductor structure;
forming a high-K gate dielectric layer on the interfacial layer;
forming a dipole metal layer comprising dopants in the high-gate dielectric layer on the high-K gate dielectric layer;
annealing the dipole metal layer;
removing the dipole metal layer;
forming a first high-K dielectric cap layer on the high-K gate dielectric layer;
forming a p-type work function adjusting layer on the high-K gate dielectric layer;
forming an n-type work function adjusting layer on the high-K gate dielectric layer;
forming a second high-K dielectric cap layer on the p-type work function adjusting layer and the n-type work function adjusting layer; and
forming a metal gate electrode on the second high-K dielectric cap layer, wherein
the p-type work function adjusting layer comprises p-doped conductive material, and
the n-type work function adjusting layer comprises n-doped conductive material.

### Claim 13 (depends on 12)

The method of claim 12, wherein the forming of the dipole metal layer comprises:
blanket depositing the dipole metal layer on the high-K gate dielectric layer; and
patterning the dipole metal layer.

### Claim 14 (depends on 12)

The method of claim 12, wherein
the high-K gate dielectric layer comprises hafnium oxide (HfO2).

### Claim 15 (depends on 14)

The method of claim 14, wherein
the dipole metal layer comprises lanthanum (La).

### Claim 16 (depends on 14)

The method of claim 14, wherein
the dipole metal layer comprises aluminum (Al) or niobium (Nb).

### Claim 17 (depends on 12)

The method of claim 12, wherein
the metal gate electrode comprises tungsten (W).

### Claim 18 (depends on 17)

The method of claim 17, wherein
the p-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

### Claim 19 (depends on 17)

The method of claim 17, wherein
the n-type work function adjusting layer comprises n-doped conductive material and has a thickness of between 35 Å and 30 Å.

### Claim 20 (depends on 12)

The method of claim 12, wherein
the first high-K dielectric cap layer and the second high-K dielectric cap layer each comprise titanium nitride (TIN).