# US 12,183,797 B2 · Profile control of channel structures for semiconductor devices

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- Number: US 12,183,797 B2
- Document ID: US12183797B2
- Status: Granted
- Kind: B2
- Application number: 17/471,863
- Filed: 2021-09-10
- Published: 2022-11-17
- Granted: 2024-12-31
- Earliest claimed: 2021-05-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semicondcutor Manufacturing Co., Ltd.
- Inventors: Chao-Wei Hsu
- Web page: https://patentgrep.com/patent/US12183797B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10P 70/20: {Cleaning during device manufacture}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10P 50/242: {of Group IV materials}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.

## Claims

### Claim 1

A semiconductor device, comprising:
a fin structure on a substrate, wherein the fin structure comprises a bottom portion on the substrate and a top portion comprising a plurality of semiconductor layers, and wherein end portions of the plurality of semiconductor layers have a recessed surface;
a gate structure wrapped around the plurality of semiconductor layers; and
a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the recessed surface of the end portions of the plurality of semiconductor layers, wherein the S/D structure extends into the end portions of the plurality of semiconductor layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a distance of the S/D structure extending into the plurality of semiconductor layer to a length of the plurality of semiconductor layers at an edge region ranges from about 5% to about 15%.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a spacer structure on the fin structure and in contact with sidewalls of the gate structure, wherein the S/D structure extends laterally beyond a sidewall surface of the spacer structure.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a distance of the S/D structure extending into the plurality of semiconductor layer is less than a width of the spacer structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of inner spacer structures between the plurality of semiconductor layers, wherein the S/D structure laterally extends beyond sidewall surfaces of the plurality of inner spacer structures.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein each of the end portions of the plurality of semiconductor layers has a V shape from a top-down view comprising a sloped recessed center region and an edge region, and wherein the S/D structure extends into the sloped recessed center region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein each of the end portions of the plurality of semiconductor layers has a sigma (Σ) shape from a top-down view comprising a center region, an edge region, and a recessed intermediate region between the center region and the edge region, and wherein the S/D structure extends into the recessed intermediate region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein each of the end portions of the plurality of semiconductor layers has a pi (Π) shape from a top-down vie\v comprising a flat recessed center region and an edge region, and wherein the S/D structure extends into the flat recessed center region.

### Claim 9

A semiconductor device, comprising:
a fin structure on a substrate, wherein the fin structure comprises a plurality of semiconductor layers;
a gate structure wrapped around each of the plurality of semiconductor layers;
a spacer structure on the fin structure and in contact with sidewalls of the gate structure; and
first and second S/D structures on opposite ends of the plurality of semiconductor layers, wherein the first and second S/D structures laterally extends below the spacer structure, and wherein a distance between the first and second S/D structures at a center region of the plurality of semiconductor layers is less than a length of the plurality of semiconductor layers at an edge region.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a ratio of the distance between the first and second S/D structures to the length of the plurality of semiconductor layers at the edge region ranges from about 70% to about 95%.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein a width of the gate structure is less than the length of the plurality of semiconductor layers at the edge region.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein a distance of the first and second S/D structures laterally extending below the spacer structure is less than a width of the spacer structure.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising a plurality of inner spacer structures between the gate structure and the first and second S/D structures, wherein the first and second S/D structures laterally extend beyond sidewall surfaces of the plurality of inner spacer structures.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein each of end portions of the plurality of semiconductor layers has a V shape, a sigma shape, or a pi (Π) shape from a top-down view, wherein each of the V, Σ, and Π shapes comprises a recessed region, and wherein the first and second S/D structures extend into the recessed region of the plurality of semiconductor layers.

### Claim 15

A semiconductor device, comprising:
a plurality of semiconductor layers on a substrate, wherein:
each of the plurality of semiconductor layers comprises a center region and an edge region;
the center region has a first length; and
the edge region has a second length greater than the first length;
a gate structure in contact with the edge region and wrapped around the edge region of the plurality of semiconductor layers; and
a source/drain (S/D) structure adjacent to end portions of the plurality of semiconductor layers, wherein the S/D structure is in contact with the center region and the end region of the plurality of semiconductor layers.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a ratio of the first length to the second length ranges from about 70% to about 95%.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a width of the gate structure is less than the second length.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, further comprising a spacer structure above the plurality of semiconductor layers and on a sidewall of the gate structure, wherein a distance of the S/D structure laterally extends below the spacer structure is less than a width of the spacer structure.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising a plurality of inner spacer structures between the gate structure and the S/D structure, wherein the S/D structure laterally extends towards the plurality of semiconductor layers beyond sidewall surfaces of the plurality of inner spacer structures.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein:
each of the end portions of the plurality of semiconductor layers has a V shape, a sigma (Σ) shape, or a pi (Π) shape from a top-down view;
each of the V, Σ, and Π shapes comprises a recessed region; and
the S/D structure extends into the recessed region of the plurality of semiconductor layers.