# US 12,183,795 B2 · Notch shape of trench gate bottom corner for better breakdown voltage of power MOSFET and IGBT with good trade off to ron and ox reliability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,795 B2 - Document ID: US12183795B2 - Status: Granted - Kind: B2 - Application number: 17/707,548 - Filed: 2022-03-29 - Published: 2022-10-06 - Granted: 2024-12-31 - Earliest claimed: 2021-04-02 - Assignees: SiEn (QingDao) Integrated Circuits Co., Ltd. - Applicants: SiEn (QingDao) Integrated Circuits Co., Ltd. - Inventors: Conghui Liu; Peng Li; Min-Hwa Chi - Web page: https://patentgrep.com/patent/US12183795B2 ## CPC - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 64/01: Manufacture or treatment - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 12/031: {of IGBTs} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 62/8325: {Silicon carbide} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present invention provides a device having a trench gate structure and a method of making the same. The device comprises a substrate, a drift region, a well region, a trench gate, a heavily-doped region, and an electrode positioned on the heavily-doped region. The structure of the device is simple to provide good VDMOS and IGBT breakdown voltages, and meanwhile take on-state resistance and reliability of oxide into account. ## Claims ### Claim 1 A device having a trench gate structure, comprising: a substrate having a first conductivity type, and the substrate having a first main surface and a second main surface opposite to the first main surface; a drift region formed on the first main surface of the substrate, the drift region having the first conductivity type, and a carrier content of the drift region being lower than that of the substrate; a well region formed on the drift region, and the well region having a second conductivity type opposite to the first conductivity type; a trench gate, the trench gate passing through the well region and reaching the drift region, a bottom corner of two sides of the trench gate having a recess expanding outwardly, and an internal angle of the recess being less than 90°; a heavily-doped region formed in the well region and at a side edge of the trench gate, and the heavily-doped region having the first conductivity type; and an electrode positioned on the heavily-doped region, and the electrode contacting with the heavily-doped region and at least partially extending in the well region. ### Claim 2 (depends on 1) The device having a trench gate structure according to claim 1, wherein the substrate comprises one of silicon, silicon carbide, germanium and gallium nitride. ### Claim 3 (depends on 1) The device having a trench gate structure according to claim 1, wherein the electrode is of a metal material. ### Claim 4 (depends on 1) The device having a trench gate structure according to claim 1, wherein the trench gate comprises a trench, a gate dielectric layer positioned at a trench sidewall and a gate material filling the trench, the gate material comprises at least one of polysilicon, metal and metal silicide, and the gate dielectric layer comprises one of silicon dioxide and silicon nitride layer. ### Claim 5 (depends on 1) The device having a trench gate structure according to claim 1, wherein the second main surface of the substrate is further formed with a drain to form a VDMOS device. ### Claim 6 (depends on 1) The device having a trench gate structure according to claim 1, wherein the second main surface of the substrate is formed with a collector region of the second conductivity type, and a surface of the collector region is formed with a collector electrode to form an IGBT device. ### Claim 7 (depends on 1) The device having a trench gate structure according to claim 1, wherein the internal angle of the recess is between 20˜70°. ### Claim 8 A method of making a device having a trench gate structure, comprising steps of: providing a substrate, the substrate having a first conductivity type, and the substrate having a first main surface and a second main surface opposite to the first main surface; forming a drift region on the first main surface of the substrate, the drift region having the first conductivity type, and a carrier content of the drift region being lower than that of the substrate; forming a well region on the drift region, and the well region having a second conductivity type opposite to the first conductivity type; forming a trench gate passing through the well region and reaching the drift region, a bottom corner of two sides of the trench gate having a recess expanding outwardly, and an internal angle of the recess being less than 90°; forming a heavily-doped region in the well region and at a side edge of the trench gate, and the heavily-doped region having the first conductivity type; and positioning an electrode on the heavily-doped region, and the electrode contacting with the heavily-doped region and at least partially extending in the well region. ### Claim 9 (depends on 8) The method of making a device having a trench gate structure according to claim 8, wherein a step of performing anisotropic trench etching along a vertical direction until being close to a desirable depth is performed at first, and then a step of performing isotropic etching at a trench bottom is performed, and the isotropic etching is performed vertically and horizontally at the same time to form the recess. ### Claim 10 (depends on 8) The method of making a device having a trench gate structure according to claim 8, wherein the internal angle of the recess is adjusted through an isotropic etching rate, an etching time and an etching temperature.