# US 12,183,791 B2 · Integrated circuit structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,183,791 B2
- Document ID: US12183791B2
- Status: Granted
- Kind: B2
- Application number: 18/309,181
- Filed: 2023-04-28
- Published: 2023-08-17
- Granted: 2024-12-31
- Earliest claimed: 2018-03-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US12183791B2

## CPC

- H10D 62/159: {Shapes}
- H10D 84/0167: {Manufacturing their channels}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An integrated circuit (IC) structure includes a substrate and a fin structure. The substrate includes a first cell region and a second cell region abutting the first cell region. The fin structure includes a first plan-view profile within the first cell region and a second plan-view profile within the second cell region. The first plan-view profile includes a first sidewall and a second sidewall opposing the first sidewall. The second plan-view profile includes a third sidewall and a fourth sidewall opposing the third sidewall. A width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a substrate comprising a first cell region and a second cell region abutting the first cell region; and
a fin structure comprising a first plan-view profile within the first cell region and a second plan-view profile within the second cell region, the first plan-view profile comprising a first sidewall and a second sidewall opposing the first sidewall, the second plan-view profile comprising a third sidewall and a fourth sidewall opposing the third sidewall, wherein a width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

### Claim 2 (depends on 1)

The IC structure of claim 1, wherein the substrate further comprises a third cell region abutting the second cell region, the fin structure further comprises a third plan-view profile within the third cell region, the third plan-view profile comprises a fifth sidewall and a sixth sidewall opposing the fifth sidewall, and a width between the fifth sidewall and the sixth sidewall is greater than a width between the third sidewall and the fourth sidewall.

### Claim 3 (depends on 1)

The IC structure of claim 1, wherein a boundary between the first plan-view profile and the second plan-view profile of the fin structure is located at a cell boundary between the first cell region and the second cell region.

### Claim 4 (depends on 1)

The IC structure of claim 1, further comprising:
an isolation gate at a cell boundary between the first cell region and the second cell region, the isolation gate overlapping a boundary between the first plan-view profile and the second plan-view profile of the fin structure.

### Claim 5 (depends on 4)

The IC structure of claim 4, wherein the isolation gate is tied to Vdd.

### Claim 6 (depends on 5)

The IC structure of claim 5, wherein the fin structure comprises p-type field-effect transistor (PFET) channel regions at opposite sides of the isolation gate.

### Claim 7 (depends on 6)

The IC structure of claim 6, wherein the PFET channel region within the first cell region has a width greater than a width of the PFET channel region within the second cell region.

### Claim 8 (depends on 4)

The IC structure of claim 4, wherein the isolation gate is tied to Vss.

### Claim 9 (depends on 8)

The IC structure of claim 8, wherein the fin structure comprises n-type field effect transistor (NFET) channel regions at opposite sides of the isolation gate.

### Claim 10 (depends on 9)

The IC structure of claim 9, wherein the NFET channel region within the first cell region has a width greater than a width of the NFET channel region within the second cell region.

### Claim 11

An IC structure, comprising:
a first transistor within a first cell region, the first transistor comprising a first channel region in a first fin, a first gate extending across the first channel region, and first source/drain epitaxial regions at opposite sides of the first gate; and
a second transistor within a second cell region abutting the first cell region, the second transistor comprising a second channel region in a second fin, a second gate extending across the second channel region, and second source/drain epitaxial regions at opposite sides of the second gate, wherein the second source/drain epitaxial regions have a maximal width smaller than a maximal width of the first source/drain epitaxial regions, wherein the first fin has a longitudinal end in direct contact with a longitudinal end of the second fin.

### Claim 12 (depends on 11)

The IC structure of claim 11, wherein the first source/drain epitaxial regions and the second source/drain epitaxial regions are of a same conductivity type.

### Claim 13 (depends on 11)

The IC structure of claim 11, wherein the first source/drain epitaxial regions are of a conductivity type different from a conductivity type of the second source/drain epitaxial regions.

### Claim 14 (depends on 11)

The IC structure of claim 11, wherein the first fin has a width greater than a width of the second fin.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein the first fin is aligned with the second fin.

### Claim 16 (depends on 11)

The IC structure of claim 11, wherein the first fin and the second fin are comprised in a continuous fin structure having a first plan-view profile within the first cell region and a second plan-view profile within the second cell region, wherein the first plan-view profile comprises a first sidewall and a second sidewall opposing the first sidewall, the second plan-view profile comprises a third sidewall and a fourth sidewall opposing the third sidewall, wherein a width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

### Claim 17

An IC structure, comprising:
a first transistor within a first cell region, the first transistor comprising a first channel region in a first fin, a first gate extending across the first channel region, and first source/drain epitaxial regions at opposite sides of the first gate; and
a second transistor within a second cell region abutting the first cell region, the second transistor comprising a second channel region in a second fin, a second gate extending across the second channel region, and second source/drain epitaxial regions at opposite sides of the first gate, wherein the first gate comprises a work function metal different from a work function metal of the second gate, wherein the first fin and the second fin are included in a continuous fin structure having a first plan-view profile within the first cell region and a second plan-view profile within the second cell region, wherein the first plan-view profile comprises a first sidewall and a second sidewall opposing the first sidewall, the second plan-view profile comprises a third sidewall and a fourth sidewall opposing the third sidewall, wherein a width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.

### Claim 18 (depends on 17)

The IC structure of claim 17, wherein the first fin and the second fin meet at a cell boundary between the first cell region and the second cell region.

### Claim 19 (depends on 17)

The IC structure of claim 17, wherein one of the first source/drain epitaxial regions has a horizontal size greater than from a horizontal size of one of the second source/drain epitaxial regions.

### Claim 20 (depends on 17)

The IC structure of claim 17, wherein the second fin has a greater length than the first fin.