# US 12,183,790 B2 · Semiconductor device structure and methods of forming the same

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- Number: US 12,183,790 B2
- Document ID: US12183790B2
- Status: Granted
- Kind: B2
- Application number: 18/229,465
- Filed: 2023-08-02
- Published: 2023-11-23
- Granted: 2024-12-31
- Earliest claimed: 2021-03-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shahaji B. More
- Web page: https://patentgrep.com/patent/US12183790B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10P 32/00: Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain epitaxial feature having a first semiconductor material, a first semiconductor layer having a first doped region and a first undoped region adjacent the first doped region, and the first doped region is in contact with the first semiconductor material. The structure further includes a second semiconductor layer disposed over the first semiconductor layer, and the second semiconductor layer includes a second doped region and a second undoped region adjacent the second doped region. The second doped region is in contact with the first semiconductor material. The structure further includes a gate electrode layer surrounding at least the first undoped region and the second undoped region.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a source/drain epitaxial feature comprising a semiconductor material including a first portion having a first thickness, a second portion having a second thickness different from the first thickness, and a third portion having a third thickness;
a first semiconductor layer comprising a first doped region and a first undoped region adjacent the first doped region, wherein the first doped region is in contact with the first portion of the semiconductor material;
a second semiconductor layer disposed over the first semiconductor layer, wherein the second semiconductor layer comprises a second doped region and a second undoped region adjacent the second doped region, and the second doped region is in contact with the second portion of the semiconductor material; and
a gate electrode layer surrounding at least the first undoped region and the second undoped region.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein the semiconductor material is doped with a dopant, and the first and second doped regions are doped with the dopant.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein the dopant is an n-type dopant or a p-type dopant, and a dopant concentration of the first doped region decreases from a first end in contact with the first portion of the semiconductor material to a second end in contact with the first undoped region.

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein the first doped region has a first width, and the second doped region has a second width substantially the same as the first width.

### Claim 5 (depends on 4)

The semiconductor device structure of claim 4, wherein the first thickness of the first portion of the semiconductor material is substantially greater than the second thickness of the second portion of the semiconductor material.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, further comprising a third semiconductor layer disposed over the second semiconductor layer, wherein the third semiconductor layer comprises a third doped region and a third undoped region adjacent the third doped region.

### Claim 7 (depends on 6)

The semiconductor device structure of claim 6, wherein the third doped region is in contact with the third portion of the semiconductor material.

### Claim 8 (depends on 7)

The semiconductor device structure of claim 7, wherein the third thickness is substantially less than the second thickness, which is substantially less than the first thickness.

### Claim 9

A semiconductor device structure, comprising:
a source/drain epitaxial feature comprising a semiconductor material;
a first semiconductor layer comprising a first channel region and a first extended source/drain region, wherein the first extended source/drain region is distinct from the source/drain epitaxial feature, wherein the first extended source/drain region is disposed between the first channel region and the semiconductor material, and the first extended source/drain region has a first width; and
a second semiconductor layer disposed over the first semiconductor layer, wherein the second semiconductor layer comprises a second channel region and a second extended source/drain region, the second extended source/drain region is disposed between the second channel region and the semiconductor material, and the second extended source/drain region has a second width different from the first width.

### Claim 10 (depends on 9)

The semiconductor device structure of claim 9, wherein the semiconductor material comprises a first portion in contact with the first extended source/drain region and a second portion in contact with the second extended source/drain region.

### Claim 11 (depends on 10)

The semiconductor device structure of claim 10, wherein the first portion of the semiconductor material has a first thickness, and the second portion of the semiconductor material has a second thickness substantially the same as the first thickness.

### Claim 12 (depends on 11)

The semiconductor device structure of claim 11, further comprises a third semiconductor layer disposed over the second semiconductor layer, wherein the third semiconductor layer comprises a third channel region and a third extended source/drain region.

### Claim 13 (depends on 12)

The semiconductor device structure of claim 12, wherein the third extended source/drain region has a third width different from the first and second widths.

### Claim 14 (depends on 13)

The semiconductor device structure of claim 13, wherein the third width is substantially greater than the second width, which is substantially greater than the first width.

### Claim 15 (depends on 14)

The semiconductor device structure of claim 14, wherein the semiconductor material further comprises a third portion in contact with the third extended source/drain region.

### Claim 16 (depends on 15)

The semiconductor device structure of claim 15, wherein the third portion of the semiconductor material has a third thickness substantially the same as the second thickness.

### Claim 17

A method, comprising:
forming a fin comprising a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and a third semiconductor layer disposed over the second semiconductor layer;
removing portions of the fin to expose a substrate portion;
depositing a first semiconductor material over the substrate portion, wherein the first semiconductor material has a first portion in contact with the first semiconductor layer, a second portion in contact with the second semiconductor layer, and a third portion in contact with the third semiconductor layer, the first portion has a first thickness, the second portion has a second thickness different from the first thickness, and the third portion has a third thickness;
heating the first semiconductor material and the first, second, and third semiconductor layers to a temperature ranging from about 800 degrees Celsius to about 1000 degrees Celsius; and
forming a gate electrode layer surrounding at least a portion of each of the first, second, and third semiconductor layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a second semiconductor material on the first semiconductor material; and
forming a third semiconductor material on the second semiconductor material.

### Claim 19 (depends on 18)

The method of claim 18, further comprising driving a dopant from the first semiconductor material into the first, second, and third semiconductor layers to form a first doped region in the first semiconductor layer, a second doped region in the second semiconductor layer, and a third doped region in the third semiconductor layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first doped region, the second doped region, and the third doped region have substantially the same width.