# US 12,183,789 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,789 B2 - Document ID: US12183789B2 - Status: Granted - Kind: B2 - Application number: 17/645,996 - Filed: 2021-12-26 - Published: 2022-04-21 - Granted: 2024-12-31 - Earliest claimed: 2020-01-17 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Daisuke Ozaki; Tohru Shirakawa; Yasunori Agata - Web page: https://patentgrep.com/patent/US12183789B2 ## CPC - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 8/422: {PN diodes having the PN junctions in mesas} - H10D 12/00: Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/129: {Cathode regions of diodes} - H10D 62/133: {Emitter regions of BJTs} - H10D 62/145: {Emitter regions of IGBTs} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/53: the imperfections being within the semiconductor body - H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10P 36/00: Gettering within semiconductor bodies - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. The diode portion includes a lifetime control region including a lifetime killer. Both the transistor portion and the diode portion include a base region of a second conductivity type on a surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate including a transistor portion and a diode portion, wherein the transistor portion includes an injection suppression region configured to suppress injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate, wherein the diode portion includes a lifetime control region including a lifetime killer, wherein both the transistor portion and the diode portion have a base region of a second conductivity type in a surface of the semiconductor substrate, wherein the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region in the surface of the semiconductor substrate, wherein the injection suppression region is not provided with the emitter region and the extraction region, wherein the lifetime control region is provided over at least a part of the injection suppression region from the diode portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a width of the lifetime control region in an arrangement direction of the transistor portion and the diode portion ranges from 20 μm to 1500 μm in the injection suppression region in a top view of the semiconductor substrate. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein a width of the injection suppression region in an arrangement direction of the transistor portion and the diode portion ranges from 20 μm to 900 μm in a top view of the semiconductor substrate. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the injection suppression region is further provided between an end portion of the diode portion in an extending direction and an outer periphery of an active region in a top view of the semiconductor substrate. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein an area of the diode portion is 10% or more of a total area of the diode portion and the injection suppression region in a top view of the semiconductor substrate. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein a total area of the diode portion ranges from 1.4% to 22% of an area of the semiconductor device in a top view of the semiconductor substrate. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein a doping concentration of the base region in the injection suppression region is equal to or less than a doping concentration of the base region of the diode portion. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein a doping concentration of the base region in the injection suppression region ranges from 1×e16 cm−3 to 5×e19 cm−3. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein a doping concentration of the base region of the diode portion ranges from 1×e16 cm−3 to 1×e18 cm−3. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein an end portion of the lifetime control region on the injection suppression region side is at a position retreated into the diode portion only by a distance of 1 μm or more and 10 μm or less from an end portion of the diode portion on the injection suppression region side. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein a doping concentration of the extraction region ranges from 5×e18 cm−3 to 5×e20 cm−3. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, further comprising: an accumulation region of a first conductivity type in the semiconductor substrate. ### Claim 13 A semiconductor device comprising: a semiconductor substrate including a transistor portion and a diode portion, wherein the transistor portion includes an injection suppression region configured to suppress injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate, wherein the diode portion includes a lifetime control region including a lifetime killer, wherein both the transistor portion and the diode portion have a base region of a second conductivity type in a surface of the semiconductor substrate, wherein the transistor portion and the injection suppression region further include an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region in the surface of the semiconductor substrate, wherein a ratio of the emitter region and the extraction region in the injection suppression region is lower than a ratio of the emitter region and the extraction region in the transistor portion, wherein, between a plurality of trench portions which extend in an extending direction of the transistor portion and the diode portion and are arranged in an arrangement direction of the transistor portion and the diode portion, the transistor portion and the injection suppression region include a plurality of mesa portions extending in the extending direction, and wherein any one of the emitter region and the extraction region is disposed in a mesa portion of the injection suppression region so as to be adjacent to each of the emitter regions disposed in a mesa portion adjacent to the transistor portion side. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the emitter region of the injection suppression region is adjacent to the extraction region in the extending direction. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein a length of the extraction region is 0.5 μm or more in an extending direction of the transistor portion and the diode portion in a top view of the semiconductor substrate. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein a length of the extraction region is 0.3 μm or more in an arrangement direction of the transistor portion and the diode portion in a top view of the semiconductor substrate. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein the base region is disposed in a portion where the emitter region and the extraction region are not disposed in a top view of the semiconductor substrate in the injection suppression region. ### Claim 18 A semiconductor device comprising: a semiconductor substrate including a transistor portion and a diode portion, wherein the transistor portion includes an injection suppression region configured to suppress injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate, wherein the diode portion includes a lifetime control region including a lifetime killer, wherein both the transistor portion and the diode portion have a base region of a second conductivity type in a surface of the semiconductor substrate, wherein the transistor portion and the injection suppression region further include an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region in the surface of the semiconductor substrate, wherein a ratio of the emitter region and the extraction region in the injection suppression region is lower than a ratio of the emitter region and the extraction region in the transistor portion, and wherein the emitter region is not disposed in a mesa portion adjacent to the diode portion in the injection suppression region.