# US 12,183,788 B2 · Semiconductor arrangement comprising a source pad, gate pad, drain pad, backside interconnect line, and backside contact, and backside conductive line and method of making

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- Number: US 12,183,788 B2
- Document ID: US12183788B2
- Status: Granted
- Kind: B2
- Application number: 18/231,847
- Filed: 2023-08-09
- Published: 2023-11-30
- Granted: 2024-12-31
- Earliest claimed: 2021-03-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Shih-Wei Peng; Jiann-Tyng Tzeng
- Web page: https://patentgrep.com/patent/US12183788B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.

## Claims

### Claim 1

A semiconductor arrangement, comprising:
a first source pad over a semiconductor layer;
a first nanosheet contacting the first source pad;
a gate pad adjacent the first nanosheet;
a first drain pad over the gate pad and contacting the first nanosheet;
a backside interconnect line under the gate pad and the first source pad;
a first backside contact contacting the first source pad;
a first backside conductive line contacting the first backside contact; and
a dielectric material between the first backside contact and the backside interconnect line.

### Claim 2 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a cap layer between the first backside contact and the first backside conductive line.

### Claim 3 (depends on 1)

The semiconductor arrangement of claim 1, wherein the dielectric material is between the first backside contact and the semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor arrangement of claim 1, wherein the first backside contact is between the semiconductor layer and the backside interconnect line.

### Claim 5 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a shallow trench isolation (STI) structure underlying the gate pad.

### Claim 6 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a cap layer underlying the backside interconnect line.

### Claim 7 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a first cap layer underlying the first backside contact; and
a second cap layer underlying the backside interconnect line, wherein the dielectric material is between the first cap layer and the second cap layer.

### Claim 8 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a second source pad formed over the semiconductor layer;
a second nanosheet contacting the second source pad; and
a second drain pad over the gate pad and contacting the second nanosheet.

### Claim 9 (depends on 8)

The semiconductor arrangement of claim 8, comprising:
a second backside contact contacting the second source pad.

### Claim 10 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a backside gate contact contacting the backside interconnect line and the gate pad.

### Claim 11

A method of forming a semiconductor arrangement, comprising:
forming a first source pad over a semiconductor layer;
forming a first nanosheet contacting the first source pad;
forming a gate pad adjacent the first nanosheet;
forming a first drain pad over the gate pad and contacting the first nanosheet;
forming a backside interconnect line under the gate pad and the first source pad; and
forming a first backside contact to connect the backside interconnect line to the gate pad.

### Claim 12 (depends on 11)

The method of claim 11, comprising:
forming a second backside contact underlying the first source pad; and
forming a backside conductive line under the second backside contact.

### Claim 13 (depends on 12)

The method of claim 12, comprising:
forming a cap layer between the backside conductive line and the second backside contact.

### Claim 14 (depends on 12)

The method of claim 12, comprising:
forming a spacer layer between the second backside contact and the backside interconnect line.

### Claim 15 (depends on 11)

The method of claim 11, wherein forming the first backside contact comprises forming the first backside contact through the semiconductor layer.

### Claim 16

A semiconductor arrangement, comprising:
a first source pad and a second source pad over a semiconductor layer;
a first nanosheet contacting the first source pad;
a second nanosheet contacting the second source pad;
a gate pad adjacent the first nanosheet;
a first drain pad over the gate pad and contacting the first nanosheet;
a second drain pad over the gate pad and contacting the second nanosheet;
a backside interconnect line under the gate pad and the first source pad;
a first backside contact contacting the first source pad; and
a second backside contact contacting the second source pad.

### Claim 17 (depends on 16)

The semiconductor arrangement of claim 16, wherein the gate pad is between the first nanosheet and the second nanosheet.

### Claim 18 (depends on 16)

The semiconductor arrangement of claim 16, wherein the backside interconnect line underlies the gate pad, the first source pad, and the second source pad.

### Claim 19 (depends on 16)

The semiconductor arrangement of claim 16, comprising:
a cap layer between the first backside contact and a backside conductive line under the first backside contact.

### Claim 20 (depends on 16)

The semiconductor arrangement of claim 16, comprising:
a shallow trench isolation (STI) structure under the gate pad.