# US 12,183,787 B2 · Semiconductor device with silicide gate fill structure

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- Number: US 12,183,787 B2
- Document ID: US12183787B2
- Status: Granted
- Kind: B2
- Application number: 17/872,925
- Filed: 2022-07-25
- Published: 2022-11-10
- Granted: 2024-12-31
- Earliest claimed: 2020-06-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Liang Cheng
- Web page: https://patentgrep.com/patent/US12183787B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/01: Manufacture or treatment
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/364: {of IGFETs}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

## Claims

### Claim 1

A method, comprising:
forming a first trench in an interlevel dielectric layer over a plurality of first semiconductor nanosheets corresponding to channel regions of a first transistor;
depositing a first gate dielectric on a bottom of the first trench;
depositing a first gate metal of the first transistor in the first trench, the first gate metal having a first material in direct physical contact with a first portion of a sidewall of first the gate dielectric in the first trench;
depositing a second gate metal in the first trench on the first gate metal, the second gate metal having a second material different from the first material and in direct physical contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric;
depositing a third gate metal in the first trench on the second gate metal and in direct physical contact with a third portion of the sidewall of the gate dielectric in the first trench above the second portion of the sidewall of the first gate dielectric, wherein the second gate metal is between the first gate metal and the third gate metal;
forming a first silicide above the third gate metal in the trench; and
filling the first trench with a first conductive gate fill material over the first gate metal, the second gate metal, the third gate metal, and the silicide, wherein an entirety of the first gate metal and an entirety of the second gate metal are below an entirety of the silicide in the first trench, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets, wherein the third gate metal, the first silicide, and the first gate fill material extend to a same height.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the first silicide includes:
forming a silicon layer in the first trench by flowing silane in the first trench; and
depositing titanium on the silicon layer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
selecting parameters for an atomic layer etching process of the first gate metal; and
prior to filling the first trench with the first conductive gate fill material, patterning the first gate metal within the first trench with the atomic layer etching process.

### Claim 4 (depends on 3)

The method of claim 3, further comprising selecting the parameters for the atomic layer etching process with an analysis model trained with a machine learning process.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a second trench in the interlevel dielectric layer over a plurality of second semiconductor nanosheets corresponding to channel regions of a second transistor;
depositing a second gate dielectric on a bottom of the second trench;
forming a second silicide over the gate dielectric in the second trench;
filling the second trench with a second conductive gate fill material, wherein the second conductive gate fill material of the second transistor is positioned closer to the bottom of the second trench than the first conductive gate fill material of the first transistor is positioned to the bottom of the first trench.

### Claim 6 (depends on 5)

The method of claim 5, further comprising, prior to depositing the first gate fill material, etching the gate dielectric from sidewalls of the first trench with an ALE process having parameters selected by an analysis model trained with a machine learning process.

### Claim 7

A method, comprising:
forming an interlevel dielectric layer in an integrated circuit;
forming a first transistor including:
forming a first trench in the interlevel dielectric layer above a plurality of first semiconductor nanosheets co;
depositing a first gate dielectric on a bottom and on sidewalls of the first trench; and
forming a first gate electrode, including:
depositing a first gate metal having a first material and positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench;
depositing a second gate metal in the first trench on the first gate metal, the second gate metal having a second material different from the first material and in direct physical contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric;
depositing a third gate metal in the first trench on the second gate metal and in direct physical contact with a third portion of the sidewall of the gate dielectric in the first trench above the second portion of the sidewall of the gate dielectric, wherein the second gate metal is between the first gate metal and the third gate metal;
depositing a first silicide in the first trench above the second gate metal; and
depositing a first conductive gate fill material positioned over the first gate metal and the first silicide in the first trench, wherein the first conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein an entirety of first gate metal and an entirety of the second gate metal are below an entirety of the first silicide in the first trench, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets, wherein the third gate metal, the first silicide, and the first gate fill material extend to a same height.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first silicide is titanium silicide.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first gate dielectric layer and the gate electrode surround the semiconductor nanosheets.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first conductive gate fill material extends higher within the first trench than the first gate dielectric.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first gate dielectric includes hafnium.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
forming a second transistor including:
forming a second trench in the interlevel dielectric layer over a plurality of second semiconductor nanosheets corresponding to channels of a second transistor;
depositing a second gate dielectric positioned on a bottom of the second trench;
forming a gate electrode, including depositing a second silicide and a second conductive gate fill material in the second trench above the second gate dielectric, the second conductive gate fill material of the second transistor being positioned closer to the bottom of the second trench than the first conductive gate fill material of the first transistor is positioned to the bottom of the first trench.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first transistor has a higher threshold voltage than the second transistor.

### Claim 14 (depends on 7)

The method of claim 7, wherein the first gate metal is titanium nitride.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first conductive gate fill material includes tungsten.

### Claim 16

A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first transistor; and
forming a first gate structure of the first transistor above the first semiconductor nanosheets including:
forming a first trench in an interlevel dielectric layer above the first semiconductor nanosheets;
forming a first gate dielectric on a bottom of the first trench;
forming a first gate metal in the first trench and having a first material in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench;
forming a second gate metal on the first gate metal in the first trench and having a second material different from the first material and in direct physical contact with a second portion of the sidewall of the first gate dielectric above the first portion of the sidewall of the first gate dielectric;
depositing a third gate metal in the first trench on the second gate metal and in direct physical contact with a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the gate dielectric, wherein the second gate metal is between the first gate metal and the third gate metal;
forming a first silicide above the second gate metal in the first trench;
forming a first conductive gate fill material over the first gate metal and the silicide, wherein the conductive gate fill material extends to a higher vertical level within the first trench than does the first gate metal, wherein an entirety of first gate metal and an entirety of the second gate metal are below an entirety of the silicide in the first trench, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets, wherein the third gate metal, the silicide, and the gate fill material extend to a same height;
forming a plurality of second semiconductor nanosheets corresponding to channel regions of a second transistor; and
forming a second gate structure of the second transistor above the second semiconductor nanosheets including:
forming a second trench in the interlevel dielectric layer above the second semiconductor nanosheets;
forming a second gate dielectric in the second trench;
forming a fourth gate metal over the second gate dielectric in the second trench;
forming a second silicide above the fourth gate metal in the second trench;
forming a second conductive gate fill material over the fourth gate metal and the second silicide in the second trench, wherein the second conductive gate fill material is positioned closer to the second nanosheets than the first conductive gate fill material is to the first nanosheets.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first gate dielectric includes hafnium.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first transistor has a higher threshold voltage than the second transistor.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the first silicide incudes:
forming a silicon layer in the first trench by flowing silane into the first trench; and
depositing titanium on the silicon layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein the third gate metal is titanium nitride.