# US 12,183,786 B2 · Multi-stack semiconductor device with zebra nanosheet structure

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- Number: US 12,183,786 B2
- Document ID: US12183786B2
- Status: Granted
- Kind: B2
- Application number: 17/536,939
- Filed: 2021-11-29
- Published: 2023-03-30
- Granted: 2024-12-31
- Earliest claimed: 2021-09-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Byounghak Hong; Seungchan Yun; Kang-ill Seo
- Web page: https://patentgrep.com/patent/US12183786B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

## Claims

### Claim 1

A multi-stack semiconductor device comprising:
a substrate;
a multi-stack transistor formed on the substrate and comprising a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor,
wherein the nanosheet transistor comprises a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers,
wherein the FinFET comprises at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and
wherein each of the lower and upper gate structures comprises:
a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and
a gate metal pattern formed on the gate oxide layer, the gate metal pattern comprising a work-function metal layer and a conductor plug.

### Claim 2 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein at least one of the lower and upper gate structures comprises an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

### Claim 3 (depends on 2)

The multi-stack semiconductor device of claim 2,
wherein the nanosheet layers comprises silicon (Si), and
wherein silicon germanium (SiGe) is formed between the nanosheet layers.

### Claim 4 (depends on 3)

The multi-stack semiconductor device of claim 3,
wherein each of the lower and upper gate structures comprises the EG oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

### Claim 5 (depends on 4)

The multi-stack semiconductor device of claim 4,
wherein the gate oxide layer comprises an interfacial layer and a high-κ layer,
wherein the interfacial layer comprises an oxide material, and
wherein the high-κ layer comprises a material with a dielectric constant higher than the oxide material of the interfacial layer.

### Claim 6 (depends on 1)

The multi-stack semiconductor device of claim 1,
wherein at least one of the lower and upper gate structures comprises an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure,
wherein a thickness of the gate oxide layer ranges 2 nm to 3 nm, and
wherein a thickness of the EG oxide layer ranges 4 nm to 5 nm.