# US 12,183,784 B2 · Semiconductor device with air gap on gate structure and method for forming the same

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- Number: US 12,183,784 B2
- Document ID: US12183784B2
- Status: Granted
- Kind: B2
- Application number: 18/334,605
- Filed: 2023-06-14
- Published: 2023-10-19
- Granted: 2024-12-31
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tien-Lu Lin; Che-Chen Wu; Chia-Lin Chuang; Yu-Ming Lin; Chia-Hao Chang
- Web page: https://patentgrep.com/patent/US12183784B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/46: comprising air gaps
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer;
an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer; and
gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the insulating capping stack comprises:
a first capping layer having the lower surface of the insulating capping stack;
a second capping layer having opposite sidewall surfaces and a lower surface covered by the first capping layer.

### Claim 3 (depends on 2)

The semiconductor device structure as claimed in claim 2, wherein the second capping layer has an upper surface that is substantially level with upper surfaces of the gate spacers.

### Claim 4 (depends on 2)

The semiconductor device structure as claimed in claim 2, wherein the first capping layer comprises a low-k material.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising a source/drain feature formed in the semiconductor substrate and adjacent to the gate electrode layer.

### Claim 6 (depends on 5)

The semiconductor device structure as claimed in claim 5, further comprising a source/drain contact structure formed over the source/drain feature.

### Claim 7 (depends on 6)

The semiconductor device structure as claimed in claim 6, further comprising:
a via structure formed over the source/drain contact structure; and
a conductive capping layer formed between the source/drain contact structure and the via structure.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising:
a gate dielectric layer between the gate spacers and the gate electrode layer and between the semiconductor substrate and the gate electrode layer.

### Claim 9 (depends on 8)

The semiconductor device structure as claimed in claim 8, wherein an upper surface of the gate dielectric layer faces and is spaced apart from the lower surface of the insulating capping stack.

### Claim 10

A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
a source/drain feature formed in the fin structure;
a first gate structure and a second gate structure across the fin structure and on both sides of the source/drain feature, wherein each of the first gate structure and the second gate structure comprises:
a gate electrode layer formed over the fin structure; and
a conductive capping layer covering the gate electrode layer;
an insulating cap structure formed over the conductive capping layer of the first gate structure; and
a conductive via structure formed over the conductive capping layer of the second gate structure,
wherein a lower surface of the insulating cap structure is higher than a lower surface of the conductive via structure, and an upper surface of the insulating cap structure is substantially level with an upper surface of the conductive via structure.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the insulating cap structure comprises:
a first capping layer; and
a second capping layer having opposite sidewall surfaces and a lower surface covered by the first capping layer.

### Claim 12 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising gate spacers that extend from opposing sidewalls of the first gate structure to opposing sidewalls of the insulating cap structure, wherein an air gap is surrounded by the gate spacers, the first gate structure, and the insulating cap structure.

### Claim 13 (depends on 12)

The semiconductor device structure as claimed in claim 12, wherein a bottom of the air gap is substantially level with the lower surface of the conductive via structure.

### Claim 14 (depends on 12)

The semiconductor device structure as claimed in claim 12, wherein a width of the air gap is equal to a width of the insulating cap structure.

### Claim 15 (depends on 10)

The semiconductor device structure as claimed in claim 10, further comprising:
an insulating layer formed over the source/drain feature formed in the fin structure and between the first gate structure and the second gate structure.

### Claim 16

A method for forming a semiconductor device structure, comprising:
forming two neighboring gate spacers over a semiconductor substrate;
forming a gate stack between the gate spacers, wherein the gate stack comprises:
a gate electrode layer; and
a conductive capping layer formed over the gate electrode layer;
covering the gate stack with a sacrificial layer, wherein upper surfaces of the gate spacers protrude above an upper surface of the sacrificial layer;
successively forming a first insulating layer and a second insulating layer to cover the upper surfaces of the gate spacers and the upper surface of the sacrificial layer;
removing portions of the first insulating layer and the second insulating layer to expose the upper surfaces of the gate spacers; and
removing the sacrificial layer after the upper surfaces of the gate spacers are exposed, so that a lower surface of the first insulating layer faces and is separated from an upper surface of the gate stack.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the sacrificial layer comprises a heat depolymerized material layer.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein the sacrificial layer is removed by an annealing process before or after the second insulating layer is formed.

### Claim 19 (depends on 16)

The method as claimed in claim 16, wherein the gate stack further comprises:
a gate dielectric layer covering opposite sidewall surfaces of the gate electrode layer and the conductive capping layer and a lower surface of the gate electrode layer.

### Claim 20 (depends on 17)

The method as claimed in claim 17, wherein after the portions of the first insulating layer and the second insulating layer are removed, opposite sidewall surfaces and a lower surface of the second insulating layer are covered by the first insulating layer.