Power semiconductor packaging and manufacturing method thereof

A power semiconductor device, comprising:

• a base comprising a substrate and an epitaxial layer disposed above the substrate, with the base comprising a unit area and a peripheral area surrounding the unit area;
• a semiconductor component surrounded by the substrate and the epitaxial layer;
• a junction layer located within the peripheral area and above the epitaxial layer;
• and
• a first electrode located on the junction layer,
• wherein the epitaxial layer comprises a doped channel located in the peripheral area and extending between the junction layer and the semiconductor component.

A method for manufacturing a power semiconductor device, comprising:

• forming a first epitaxial layer above a substrate;
• implanting doping ions into a portion of the first epitaxial layer to form a first doped channel;
• forming a second epitaxial layer on the first epitaxial layer;
• implanting the doping ions into a portion of the second epitaxial layer to form a second doped channel above the first doped channel;
• forming a junction layer above the second doped channel;
• and
• forming a first electrode on the junction layer,
• wherein the first and second doped channels extend between the junction layer and the substrate.