# US 12,183,778 B2 · Semiconductor structures having deep trench capacitor and methods for manufacturing the same

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- Number: US 12,183,778 B2
- Document ID: US12183778B2
- Status: Granted
- Kind: B2
- Application number: 17/888,749
- Filed: 2022-08-16
- Published: 2024-02-22
- Granted: 2024-12-31
- Earliest claimed: 2022-08-16
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Szu-Yu Hou; Li-Han Lin
- Web page: https://patentgrep.com/patent/US12183778B2

## CPC

- H10D 1/696: {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688)}
- H10B 12/01: {Manufacture or treatment}
- H10B 12/033: {the capacitor extending over the transistor}
- H10B 12/0387: {Making the trench}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching}
- H10D 1/716: {having vertical extensions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate having a first surface;
a plurality of layers disposed on the first surface of the substrate, including:
a first nitride layer disposed on the first surface of the substrate;
a first silicon-containing layer disposed on the first nitride layer;
an intermediate nitride layer disposed on the first silicon-containing layer;
a second silicon-containing layer disposed on the intermediate nitride layer; and
a second nitride layer disposed on the second silicon-containing layer;
a trench capacitor penetrating the plurality of layers and in contact with the substrate, wherein the trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and wherein the first lateral surface has a slope different from that of the second lateral surface;
wherein a top surface of the first nitride layer is exposed from the first silicon-containing layer, and the top surface of the first nitride layer is in contact with the trench capacitor.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first portion of the trench capacitor is surrounded by the first silicon-containing layer and the second portion of the trench capacitor is surrounded by the second silicon-containing layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first portion of the trench capacitor has a uniform width.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the second portion of the trench capacitor has a width decreasing toward the first nitride layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the second portion of the trench capacitor has a minimum width at an interface between the first silicon-containing layer and the intermediate nitride layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the first silicon-containing layer includes a first region adjacent to the first nitride layer and a second region on the first region, wherein the first region of the first silicon-containing layer has a first doping concentration, and the second region of the first silicon-containing layer has a second doping concentration different from the first doping concentration.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the second doping concentration is greater than the first doping concentration.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the first region of the first silicon-containing layer has a thickness greater than that of the second region of the first silicon-containing layer.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the first silicon-containing layer includes a material different from that of the second silicon-containing layer.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the first silicon-containing layer includes borophosphosilicate glass (BPSG) and the second silicon-containing layer includes tetraethoxysilane (TEOS).

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of a height of the trench capacitor to a width of the trench capacitor is greater than 25.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate includes a conductive region in contact with the trench capacitor.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the conductive region of the substrate includes tungsten (W).

### Claim 14 (depends on 1)

The semiconductor structure of claim 1, wherein the trench capacitor comprises:
a first conductive layer adjacent to the plurality of layers;
a first dielectric layer disposed on the first conductive layer;
an intermediate conductive layer disposed on the first dielectric layer and in contact with the substrate;
a second dielectric layer disposed on the intermediate conductive layer; and
a second conductive layer disposed on the second dielectric layer.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein the trench capacitor further comprises a polysilicon contact disposed on the second conductive layer.