# US 12,183,775 B2 · Integrated circuit with FEOL resistor

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- Number: US 12,183,775 B2
- Document ID: US12183775B2
- Status: Granted
- Kind: B2
- Application number: 18/448,111
- Filed: 2023-08-10
- Published: 2023-12-14
- Granted: 2024-12-31
- Earliest claimed: 2020-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tien-Chien Huang; Ruey-Bin Sheen; Chih-Hsien Chang
- Web page: https://patentgrep.com/patent/US12183775B2

## CPC

- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10D 84/817: {Combinations of field-effect devices and resistors only}
- H10W 44/401: {Resistive arrangements (H10W44/20, H10W42/80 take precedence)}
- H10D 1/47: Resistors having no potential barriers
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.

## Claims

### Claim 1

A method, comprising:
forming a shallow trench isolation (STI) region in a semiconductor substrate to define an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region;
forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region;
forming first source/drain regions in the active region and second source/drain regions in the passive region;
after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate;
forming an interlayer dielectric (ILD) layer over the metal gate structure and the metal resistor structure;
etching the ILD layer to form contact openings in the ILD layer, wherein the contact openings expose one region of the metal gate structure but two regions of the metal resistor structure; and
depositing a metal material into the contact openings to form a gate contact over the metal gate structure and two resistor contacts over the metal resistor structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming source/drain contacts on the first source/drain regions but not on the second source/drain regions.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a first metal line over a first one of the two resistor contacts and a second metal line over a second one of the two resistor contacts.

### Claim 4 (depends on 1)

The method of claim 1, wherein after forming the first and second source/drain regions, replacing the first sacrificial gate structure with the metal gate structure and the second sacrificial gate structure with the metal resistor structure comprises:
forming a single continuous metal gate strip extending along a first direction, and overlapping the active region and the passive region; and
performing a gate cut process on the single continuous metal gate strip thereby forming the metal gate structure and the metal resistor structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein the performing the gate cut process on the single continuous metal gate strip thereby forming the metal gate structure and the metal resistor structure comprises:
etching the single continuous metal gate strip.

### Claim 6 (depends on 1)

The method of claim 1, wherein the two resistor contacts are formed of tungsten or copper.

### Claim 7 (depends on 1)

The method of claim 1, wherein the metal resistor structure comprises a high-k dielectric layer and a metal structure over the high-k dielectric layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the metal gate structure comprises a high-k gate dielectric layer, and the high-k gate dielectric layer is formed of a same material as the high-k dielectric layer of the metal resistor structure.

### Claim 9 (depends on 7)

The method of claim 7, wherein the high-k dielectric layer lines a bottom surface and opposite sidewalls of the metal structure.

### Claim 10 (depends on 7)

The method of claim 7, wherein the high-k dielectric layer of the metal resistor structure has a U-shaped cross section.

### Claim 11

A method, comprising:
forming a first sacrificial gate structure over an active region in a semiconductor substrate and a second sacrificial gate structure over a passive region;
forming first source/drain regions in the active region and second source/drain regions in the passive region;
after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate;
forming a first interlayer dielectric (ILD) layer over the metal gate structure and the metal resistor structure;
etching the first ILD layer to form contact openings in the ILD layer, wherein the contact openings expose one region of the metal gate structure and two regions of the metal resistor structure; and
depositing a metal material into the contact openings to form a gate contact over the metal gate structure and two resistor contacts over the metal resistor structure.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming source/drain contacts on the first source/drain regions but not on the second source/drain regions.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
forming a second ILD layer over the two resistor contacts and the gate contact.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
forming a first metal line in the second ILD layer over a first one of the two resistor contacts and a second metal line over a second one of the two resistor contacts.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
removing, by a planarization process, a top surface of the metal material from above a top surface of the second ILD layer.

### Claim 16

A method, comprising:
forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region;
forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region;
forming first source/drain regions in the active region and second source/drain regions in the passive region;
after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate;
forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure; and
electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts;
wherein forming the first gate contact over the metal gate structure, and the pair of resistor contacts over the metal resistor structure comprises:
forming an interlayer dielectric (ILD) layer over the metal gate structure and the metal resistor structure;
etching the ILD layer thereby forming contact openings in the ILD layer, wherein the contact openings expose one region of the metal gate structure and two regions of the metal resistor structure; and
depositing a metal material into the contact openings thereby forming the first gate contact over the metal gate structure and the pair of resistor contacts over the metal resistor structure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming source/drain contacts on the first source/drain regions but not on the second source/drain regions.

### Claim 18 (depends on 16)

The method of claim 16, wherein electrically coupling the set of metal lines with the metal resistor structure by the pair of resistor contacts comprises:
forming a first metal line of the set of metal lines over a first one of the pair of resistor contacts and a second metal line of the set of metal lines over a second one of the pair of resistor contacts.

### Claim 19 (depends on 16)

The method of claim 16, wherein after forming the first and second source/drain regions, replacing the first sacrificial gate structure with the metal gate structure and the second sacrificial gate structure with the metal resistor structure comprises:
forming a single continuous metal gate strip extending along a first direction, and overlapping the active region and the passive region; and
etching the single continuous metal gate strip thereby forming the metal gate structure and the metal resistor structure.

### Claim 20 (depends on 16)

The method of claim 16, wherein the pair of resistor contacts are formed of tungsten or copper.