# US 12,183,764 B2 · Channel pattern design to improve carrier transfer efficiency

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- Number: US 12,183,764 B2
- Document ID: US12183764B2
- Status: Granted
- Kind: B2
- Application number: 17/735,420
- Filed: 2022-05-03
- Published: 2023-08-10
- Granted: 2024-12-31
- Earliest claimed: 2022-02-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yung-Chang Chang; Shih-Wei Lin; Te-Hsien Hsieh; Jung-I Lin
- Web page: https://patentgrep.com/patent/US12183764B2

## CPC

- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/8027: {Geometry of the photosensitive area}
- H10F 39/8033: {Photosensitive area}
- H10F 39/8037: {the integrated elements comprising a transistor}
- H10F 39/807: {Pixel isolation structures}
- H10F 39/811: {Interconnections}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.

## Claims

### Claim 1

An image sensor integrated chip, comprising:
a photodiode region disposed within a substrate comprising a first semiconductor material region;
a second semiconductor material region disposed onto the substrate;
a patterned doped layer arranged between the substrate and the second semiconductor material region; and
wherein the second semiconductor material region comprises a sidewall connected to a bottom surface of the second semiconductor material region, the sidewall extending through the patterned doped layer and the bottom surface being directly over the photodiode region.

### Claim 2 (depends on 1)

The image sensor integrated chip of claim 1, wherein a sidewall of the patterned doped layer laterally contacts the sidewall of the second semiconductor material region along an interface that is directly over the photodiode region.

### Claim 3 (depends on 1)

The image sensor integrated chip of claim 1, wherein the substrate comprises sidewalls and a horizontally extending surface defining a recess within an upper surface of the substrate, the second semiconductor material region being disposed within the recess.

### Claim 4 (depends on 3)

The image sensor integrated chip of claim 3, further comprising:
a capping layer arranged on the second semiconductor material region and directly between the sidewalls of the substrate.

### Claim 5 (depends on 1)

The image sensor integrated chip of claim 1, wherein the patterned doped layer comprises boron.

### Claim 6 (depends on 1)

The image sensor integrated chip of claim 1, wherein the second semiconductor material region vertically extends to below a bottom of the patterned doped layer.

### Claim 7 (depends on 1)

The image sensor integrated chip of claim 1, wherein the patterned doped layer is both laterally and vertically between the first semiconductor material region and the second semiconductor material region.

### Claim 8 (depends on 1)

The image sensor integrated chip of claim 1, wherein the patterned doped layer is a same semiconductor material region as the first semiconductor material region.

### Claim 9 (depends on 1)

The image sensor integrated chip of claim 1, wherein the photodiode region comprises:
a first doped region having a first doping type, wherein the first doped region is directly below the bottom surface of the second semiconductor material region; and
a second doped region having a second doping type, wherein the second doped region comprises a vertically extending second doped region coupled to a horizontally extending second doped region that contacts a bottom of the first doped region.

### Claim 10

An image sensor integrated chip, comprising:
a photodiode region disposed within a silicon substrate;
a patterned doped silicon layer disposed on the silicon substrate, the patterned doped silicon layer having sidewalls directly overlying the photodiode region;
a germanium region disposed onto the patterned doped silicon layer, wherein the germanium region comprises a protrusion extending outward from a lower surface of the germanium region to directly between the sidewalls of the patterned doped silicon layer;
a first interconnect coupled to a doped region, the doped region extending from the first interconnect to the photodiode region; and
a second interconnect coupled to a first doped contact region, the first doped contact region disposed within the germanium region directly over both the photodiode region and the protrusion of the germanium region.

### Claim 11 (depends on 10)

The image sensor integrated chip of claim 10, further comprising:
a dielectric structure disposed over the germanium region and the silicon substrate, wherein the dielectric structure laterally surrounds the first interconnect and the second interconnect.

### Claim 12 (depends on 10)

The image sensor integrated chip of claim 10, further comprising:
a first dielectric structure disposed below the silicon substrate and surrounding the first interconnect; and
a second dielectric structure disposed over the germanium region and surrounding the second interconnect.

### Claim 13 (depends on 10)

The image sensor integrated chip of claim 10,
wherein the patterned doped silicon layer comprises a plurality of sidewalls laterally separated from one another by the patterned doped silicon layer, the plurality of sidewalls defining a plurality of separate channel openings extending through the patterned doped silicon layer; and
wherein the germanium region extends through the plurality of separate channel openings to contact the silicon substrate.

### Claim 14 (depends on 13)

The image sensor integrated chip of claim 13, wherein the plurality of separate channel openings are disposed in an array and are separated from one another along a first direction and along a second direction that is perpendicular to the first direction, the first direction and the second direction being parallel to the lower surface of the germanium region.

### Claim 15 (depends on 10)

The image sensor integrated chip of claim 10, wherein the protrusion has a smaller width than the photodiode region.

### Claim 16

A method of forming an image sensor integrated chip, comprising:
forming a photodiode region within a substrate comprising a first semiconductor material region;
forming a doped layer along an outer surface of the substrate and over the photodiode region;
patterning the doped layer to form a patterned doped layer having one or more sidewalls that define one or more channel openings that extend through the patterned doped layer directly over the photodiode region; and
forming a second semiconductor material region onto the patterned doped layer and within the one or more channel openings.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the photodiode region comprises:
performing a first implantation process to form a first doped region having a first doping type; and
performing a second implantation process to form a second doped region having a second doping type, the second doped region below the first doped region.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second doped region comprises a horizontally extending second doped region extending below a bottom of the second semiconductor material region and a vertically extending second doped region extending along a sidewall of the second semiconductor material region.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
patterning the substrate to form a recess within an upper surface of the substrate;
forming the second semiconductor material region within the recess; and
performing a planarization process to remove excess of the second semiconductor material region from over the substrate.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
performing an etching process to recess the second semiconductor material region below an upper surface of the substrate;
forming a capping layer over the second semiconductor material region; and
forming a doped contact region within the capping layer.