# US 12,183,754 B2 · Single-photon avalanche diodes with deep trench isolation

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- Number: US 12,183,754 B2
- Document ID: US12183754B2
- Status: Granted
- Kind: B2
- Application number: 17/410,025
- Filed: 2021-08-24
- Published: 2023-03-02
- Granted: 2024-12-31
- Earliest claimed: 2021-08-24
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Ping Zheng; Eng Huat Toh; Eric Linardy; Kiok Boone Elgin Quek
- Web page: https://patentgrep.com/patent/US12183754B2

## CPC

- H10F 39/807: {Pixel isolation structures}
- H10F 30/2255: {in which the active layers form heterostructures, e.g. SAM structures}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8057: {Optical shielding}
- H10F 30/225: the potential barrier working in avalanche mode, e.g. avalanche photodiodes
- H10F 39/8063: {Microlenses}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor layer having a first well and a second well defining a p-n junction with the first well, and an interlayer dielectric layer on the semiconductor layer. A deep trench isolation region includes a conductor layer and a dielectric liner. The conductor layer penetrates through the semiconductor layer and the interlayer dielectric layer. The conductor layer has a first end, a second end, and a sidewall that connects the first end to the second end. The dielectric liner is arranged to surround the sidewall of the conductor layer. A metal feature is connected to the first end of the conductor layer.

## Claims

### Claim 1

A structure for a single-photon avalanche detector, the structure comprising:
a plurality of semiconductor layers including a first well, a second well defining a p-n junction with the first well, a first surface, and a second surface opposite from the first surface;
a micro-lens adjacent to the second surface of the semiconductor layers;
an interlayer dielectric layer on the first surface of the semiconductor layers;
a deep trench isolation region including a conductor layer and a dielectric liner, the conductor layer including a first portion in the semiconductor layers and a second portion in the interlayer dielectric layer, the conductor layer having a first end, a second end opposite from the first end, and a sidewall that connects the first end to the second end, the second end of the conductor layer coplanar with the second surface of the semiconductor layers, and the dielectric liner arranged to surround the sidewall of the conductor layer; and
a metal feature directly connected to the first end of the conductor layer,
wherein the second surface of the semiconductor layers is free of metal.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the metal feature is a first wire, and the second portion of the conductor layer is connected at the first end to the first wire.

### Claim 3 (depends on 2)

The structure of claim 2 further comprising:
a contact in the interlayer dielectric layer; and
a second wire connected by the contact to the first well.

### Claim 4 (depends on 1)

The structure of claim 1 wherein the second end of the conductor layer is free of the dielectric liner.

### Claim 5 (depends on 1)

The structure of claim 1 wherein the semiconductor layers have a conductivity type, and at least one of the semiconductor layers has a higher dopant concentration than another of the semiconductor layers.

### Claim 6 (depends on 1)

The structure of claim 1 wherein the semiconductor layers include a trench, the conductor layer and the dielectric liner are positioned in the trench, and further comprising:
a doped semiconductor layer inside the trench,
wherein the doped semiconductor layer defines a pinning layer that is positioned between the dielectric liner and the semiconductor layers surrounding the trench, and the metal feature is directly connected to the doped semiconductor layer.

### Claim 7 (depends on 6)

The structure of claim 6 wherein the dielectric liner is positioned between the doped semiconductor layer and the sidewall of the conductor layer.