# US 12,183,747 B2 · Wiring layer and manufacturing method therefor

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- Number: US 12,183,747 B2
- Document ID: US12183747B2
- Status: Granted
- Kind: B2
- Application number: 18/436,245
- Filed: 2024-02-08
- Published: 2024-06-06
- Granted: 2024-12-31
- Earliest claimed: 2014-10-01
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yutaka Okazaki; Tomoaki Moriwaka; Shinya Sasagawa; Takashi Ohtsuki
- Web page: https://patentgrep.com/patent/US12183747B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10D 30/0312: {characterised by the gate electrodes}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

## Claims

### Claim 1

A semiconductor device comprising:
a stack of plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor,
wherein the stack of the plurality of insulating films comprises a first opening,
wherein the second conductor is provided under the stack of the plurality of insulating films,
wherein the first conductor is in contact with the second conductor at a bottom of the first opening,
wherein the third conductor is provided in the stack of the plurality of insulating films,
wherein the fourth conductor is provided over the stack of the plurality of insulating films,
wherein the first conductor is in contact with a side surface of the third conductor,
wherein the first conductor is in contact with the fourth conductor,
wherein the first conductor is not in contact with the fifth conductor,
wherein the stack of the plurality of insulating films comprises a first insulating film, a second insulating film, and a third insulating film,
wherein the first insulating film has a region which is in contact with a bottom surface of the fifth conductor,
wherein the second insulating film has a region which is in contact with a top surface of the first insulating film, and a region which is in contact with a first side surface of the fifth conductor, and
wherein the third insulating film has a region which is in contact with a top surface of the second insulating film, a region which is in contact with a second side surface of the fifth conductor, and a region which is in contact with a top surface of the fifth conductor.

### Claim 2 (depends on 1)

An electronic appliance comprising the semiconductor device according to claim 1.

### Claim 3

A semiconductor device comprising:
a silicon substrate, a stack of plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor,
wherein a channel formation region of a transistor is provided in the silicon substrate,
wherein the stack of the plurality of insulating films is provided over the silicon substrate,
wherein the stack of the plurality of insulating films comprises a first opening,
wherein the second conductor is provided over the silicon substrate and under the stack of the plurality of insulating films,
wherein the first conductor is in contact with the second conductor at a bottom of the first opening,
wherein the third conductor is provided in the stack of the plurality of insulating films,
wherein the fourth conductor is provided over the stack of the plurality of insulating films,
wherein the first conductor is in contact with a side surface of the third conductor,
wherein the first conductor is in contact with the fourth conductor,
wherein the first conductor is not in contact with the fifth conductor,
wherein the stack of the plurality of insulating films comprises a first insulating film, a second insulating film, and a third insulating film,
wherein the first insulating film has a region which is in contact with a bottom surface of the fifth conductor,
wherein the second insulating film has a region which is in contact with a top surface of the first insulating film, and a region which is in contact with a first side surface of the fifth conductor, and
wherein the third insulating film has a region which is in contact with a top surface of the second insulating film, a region which is in contact with a second side surface of the fifth conductor, and a region which is in contact with a top surface of the fifth conductor.

### Claim 4 (depends on 3)

An electronic appliance comprising the semiconductor device according to claim 3.