# US 12,183,743 B2 · Semiconductor device

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- Number: US 12,183,743 B2
- Document ID: US12183743B2
- Status: Granted
- Kind: B2
- Application number: 18/231,902
- Filed: 2023-08-09
- Published: 2023-11-30
- Granted: 2024-12-31
- Earliest claimed: 2009-07-31
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei Yamazaki; Hiroki Ohara; Toshinari Sasaki; Kosei Noda; Hideaki Kuwabara
- Web page: https://patentgrep.com/patent/US12183743B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)}
- G02F 1/1337: Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- G02F 1/136277: {formed on a semiconductor substrate, e.g. of silicon}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

## Claims

### Claim 1

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a first wiring, a second wiring, and a third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is electrically connected to the third wiring, and
wherein a signal is applied to a gate of the fourth transistor, a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor.

### Claim 2

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and
a first wiring, a second wiring, and a third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal,
wherein one of a source and a drain of the eighth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a gate of the third transistor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is electrically connected to the third wiring, and
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor, and
wherein a signal is applied to a gate of the fourth transistor, a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor.

### Claim 3

A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and
a first wiring, a second wiring, and a third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to a second output terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the second output terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a first output terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first output terminal,
wherein one of a source and a drain of the eighth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein a gate of the eighth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a gate of the third transistor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein a gate of the seventh transistor is electrically connected to the third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the fifth transistor comprises an oxide semiconductor in a channel formation region, and
wherein the third transistor comprises an oxide semiconductor in a channel formation region, and
wherein a signal is applied to a gate of the fourth transistor, a first gate of the fifth transistor, a second gate of the fifth transistor, and a gate of the sixth transistor.