# US 12,183,742 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,742 B2 - Document ID: US12183742B2 - Status: Granted - Kind: B2 - Application number: 18/600,403 - Filed: 2024-03-08 - Published: 2024-07-25 - Granted: 2024-12-31 - Earliest claimed: 2019-10-02 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yoon Tae Hwang; Sunjung Lee; Heonbok Lee; Geunwoo Kim; Wandon Kim - Web page: https://patentgrep.com/patent/US12183742B2 ## CPC - H10D 84/853: {comprising FinFETs} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} - H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - H10W 20/021: {of interconnections within wafers or substrates} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/076: {in via holes or trenches} - H10W 20/083: {the openings being via holes penetrating underlying conductors} - H10W 20/4432: {the principal metal being a noble metal, e.g. gold} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns. ## Claims ### Claim 1 A semiconductor device, comprising: a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including metallic elements, wherein a thickness of the first interface layer and a thickness of the second interface layer are different from each other. ### Claim 2 (depends on 1) The device of claim 1, wherein the first and second interface layers include different metallic elements from each other, wherein the thickness of the first interface layer is greater than the thickness of the second interface layer. ### Claim 3 (depends on 2) The device of claim 2, wherein the first interface layer is disposed on a PMOSFET region. ### Claim 4 (depends on 2) The device of claim 2, further comprising: an interlayer insulating layer covering the first and second source/drain patterns, wherein the first contact plug includes a first portion, which is buried in the first source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion, wherein the second contact plug includes a third portion, which is buried in the second source/drain pattern, and a fourth portion, which penetrates the interlayer insulating layer and is connected to the third portion, wherein a width of a top portion of the first portion is smaller than a width of a top portion of the third portion. ### Claim 5 (depends on 1) The device of claim 1, wherein the first and second interface layers include same metallic elements, wherein the thickness of the first interface layer is smaller than the thickness of the second interface layer. ### Claim 6 (depends on 5) The device of claim 5, wherein the second interface layer is disposed on a NMOSFET region. ### Claim 7 (depends on 5) The device of claim 5, further comprising: an interlayer insulating layer covering the first and second source/drain patterns, wherein the first contact plug includes a first portion, which is buried in the first source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion, wherein the second contact plug includes a third portion, which is buried in the second source/drain pattern, and a fourth portion, which penetrates the interlayer insulating layer and is connected to the third portion, wherein a width of a top portion of the first portion is greater than a width of a top portion of the third portion. ### Claim 8 (depends on 1) The device of claim 1, the first and second interface layers include at least one of titanium silicide (TiSi), tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), or tantalum silicide (TaSi). ### Claim 9 (depends on 1) The device of claim 1, further comprising: an interlayer insulating layer covering the first and second source/drain patterns, wherein an uppermost surface of the first interface layer contacts directly with a first bottom surface of the interlayer insulating layer, wherein an uppermost surface of the second interface layer contacts directly with a second bottom surface of the interlayer insulating layer. ### Claim 10 (depends on 9) The device of claim 9, wherein a width of the bottom surface of the interlayer insulating layer is greater than the thickness of the first interface layer and the thickness of the second interface layer. ### Claim 11 (depends on 1) The device of claim 1, wherein a lowermost surface of the first interface layer and a lowermost surface of the second interface layer are located between an upper surface and a lower surface of a lowermost semiconductor pattern of the vertically-stacked semiconductor patterns. ### Claim 12 A semiconductor device, comprising: a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; a second interface layer interposed between the second source/drain pattern and the second contact plug; and interlayer insulating layers covering the first and second source/drain patterns, wherein two portions of the first contact plug are continuously connected to each other and two portions of the second contact plug are continuously connected to each other, wherein the first and second interface layers including different metallic elements from each other. ### Claim 13 (depends on 12) The device of claim 12, wherein each of the first contact plug and the second contact plug does not include interfacial surface therebetween. ### Claim 14 (depends on 12) The device of claim 12, wherein the interlayer insulating layers include a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer, wherein the first interface layer has a surface that is aligned to a first inner side surface of the third interlayer insulating layer. ### Claim 15 (depends on 14) The device of claim 14, wherein the second interface layer has a surface that is aligned to a second inner side surface of the third interlayer insulating layer. ### Claim 16 (depends on 12) The device of claim 12, wherein the interlayer insulating layers include a first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer, wherein an uppermost surface of the first interface layer contacts directly with a first bottom surface of the third interlayer insulating layer, wherein an uppermost surface of the second interface layer contacts directly with a second bottom surface of the third interlayer insulating layer. ### Claim 17 (depends on 12) The device of claim 12, wherein a lowermost surface of the first interface layer and a lowermost surface of the second interface layer are located between an upper surface and a lower surface of a lowermost semiconductor pattern of the vertically-stacked semiconductor patterns. ### Claim 18 A semiconductor device, comprising: a substrate having a first active region and a second active region; a first channel pattern on the first active region, and a second channel pattern on the second active region, and each of the first channel pattern and the second channel pattern including vertically-stacked semiconductor patterns; a gate electrode extended in a first direction to cross the first and second channel patterns; a first source/drain pattern disposed at a first side of the gate electrode and connected to the first channel pattern; a second source/drain pattern disposed at a second side of the gate electrode and connected to the second channel pattern, and having a different conductivity type from the first source/drain pattern; an interlayer insulating layer covering the gate electrode, the first source/drain pattern, and the second source/drain pattern; a first contact plug including a first portion, which is buried in the first source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion; a second contact plug including a third portion, which is buried in the second source/drain pattern, and a fourth portion, which penetrates the interlayer insulating layer and is connected to the third portion; a first interface layer interposed between the first portion and the first source/drain pattern; and a second interface layer interposed between the third portion and the second source/drain pattern, the first and second interface layers including different elements from each other, wherein the first and second interface layers include at least one of titanium silicide (TiSi), tungsten silicide (WSi), cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), or tantalum silicide (TaSi), wherein a thickness of the first interface layer and a thickness of the second interface layer are different from each other. ### Claim 19 (depends on 18) The device of claim 18, wherein a top surface of the first source/drain pattern, a top surface of the first interface layer and a top surface of the first portion are substantially coplanar. ### Claim 20 (depends on 18) The device of claim 18, wherein a top surface of the second source/drain pattern, a top surface of the second interface layer and a top surface of the third portion are substantially coplanar.