# US 12,183,741 B2 · Semiconductor device

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- Number: US 12,183,741 B2
- Document ID: US12183741B2
- Status: Granted
- Kind: B2
- Application number: 18/239,241
- Filed: 2023-08-29
- Published: 2023-12-14
- Granted: 2024-12-31
- Earliest claimed: 2019-05-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sungmin Kim; Daewon Ha
- Web page: https://patentgrep.com/patent/US12183741B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of semiconductor patterns spaced apart and stacked in a first direction;
a gate electrode covering each of the semiconductor patterns;
source/drain patterns distanced in a second direction perpendicular to the first direction with the semiconductor patterns interposed therebetween, the source/drain patterns include a conductive impurity;
a power rail spaced apart in the first direction from the source/drain patterns; and
a first contact connected to at least one of the source/drain patterns and the power rail,
wherein:
the gate electrode is spaced apart from the power rail in the first direction with the semiconductor patterns interposed therebetween,
the first contact is interposed between at least one of the source/drain patterns and the power rail,
the first contact is in contact with at least one of the source/drain patterns, and
the contact surface between the first contact and at least one of the source/drain patterns is closer to the power rail than the top surface of the semiconductor pattern that is closest to the power rail among the semiconductor patterns.

### Claim 2 (depends on 1)

The device of claim 1,
wherein the source/drain pattern includes a first portion adjacent to each side surface of the semiconductor patterns and a second portion protruding above a top surface of a semiconductor pattern positioned closest to the power rail among semiconductor patterns, and
wherein the width of the second portion in the second direction is greater than that of the first portion.

### Claim 3 (depends on 1)

The device of claim 1,
further comprising a gate spacer on the sidewall of the gate electrode,
wherein the source/drain patterns overlap the gate spacer in the first direction.

### Claim 4 (depends on 1)

The device of claim 1,
wherein the power rail extends in the second direction.

### Claim 5 (depends on 1)

The device of claim 1,
wherein the power rail overlaps the source/drain patterns in the first direction.

### Claim 6 (depends on 1)

The device of claim 1,
further comprising a second contact spaced apart from the power rail in a first direction with the source/drain pattern interposed therebetween.

### Claim 7 (depends on 6)

The device of claim 6, wherein a height of the first contact in the first direction is smaller than a height of the second contact in the first direction.

### Claim 8

A semiconductor device, comprising:
a plurality of semiconductor patterns spaced apart and stacked in a first direction;
a gate electrode covering each of the semiconductor patterns;
source/drain patterns distanced in a second direction perpendicular to the first direction with the semiconductor patterns interposed therebetween, each of the source/drain patterns having a first surface and a second surface facing each other along the first direction;
a power rail on the first surface of the source/drain pattern;
a first contact situated between the first surface of the source/drain pattern and the power rail; and
a second contact located on the second surface of the source/drain pattern,
wherein:
both the first contact and the second contact are in contact with the source/drain pattern and are spaced apart in the first direction with the source/drain pattern interposed therebetween;
the source/drain pattern comprises a semiconductor material containing conductive impurities.

### Claim 9 (depends on 8)

The device of claim 8,
wherein the first surface of the source/drain pattern is closer to the power rail than a top surface of a semiconductor pattern located closest to the power rail among the semiconductor patterns.

### Claim 10 (depends on 8)

The device of claim 8,
wherein the source/drain pattern has a maximum width in the second direction at a level higher than a top surface of a semiconductor pattern positioned closest to the power rail among the semiconductor patterns.

### Claim 11 (depends on 8)

The device of claim 8,
wherein the second surface of the source/drain pattern is closer to the power rail than an upper surface of the semiconductor pattern located farthest from the power rail among the semiconductor patterns.

### Claim 12 (depends on 8)

The device of claim 8,
wherein a bottom surface of the first contact adjacent to the first surface of the source/drain pattern has a larger width in the second direction than a top surface of the second contact adjacent to the second surface of the source/drain pattern.

### Claim 13 (depends on 8)

The device of claim 8,
wherein the source/drain pattern includes a first portion adjacent to each side surface of the semiconductor patterns and a second portion protruding above a top surface of a semiconductor pattern positioned closest to the power rail among semiconductor patterns, and
wherein the second portion having a width in the second direction that is greater than that of the first portion.

### Claim 14 (depends on 8)

The device of claim 8,
wherein the power rail extends in the first direction, and each of the source/drain patterns at least partially overlaps the power rail when viewed from a plan view.

### Claim 15

A semiconductor device, comprising:
a plurality of semiconductor patterns spaced apart and stacked in a first direction;
a gate electrode covering each of the semiconductor patterns;
source/drain patterns distanced in a second direction perpendicular to the first direction with the semiconductor patterns interposed therebetween, the source/drain patterns including a conductive impurity;
a power rail on the source/drain patterns;
a first contact situated between at least one of the source/drain patterns and the power rail and in contact with at least one of the source/drain patterns; and
a second contact in contact with the gate electrode,
wherein:
the semiconductor patterns, the gate electrode, and the source/drain patterns constitute a transistor,
and with respect to the transistor, both the first contact and the second contact are spaced apart in the first direction with the transistor interposed therebetween.

### Claim 16 (depends on 15)

The device of claim 15,
wherein the source/drain pattern includes a first portion adjacent to each side surface of the semiconductor patterns and a second portion protruding above a top surface of a semiconductor pattern positioned closest to the power rail among semiconductor patterns, and
wherein the second portion having a width in the second direction that is greater than that of the first portion.

### Claim 17 (depends on 15)

The device of claim 15, wherein the power rail overlaps the semiconductor patterns in the first direction.

### Claim 18 (depends on 15)

The device of claim 15, wherein the source/drain pattern has a first surface and a second surface facing along the first direction,
wherein the first surface of the source/drain pattern is closer to the power rail than a top surface of a semiconductor pattern located closest to the power rail among the semiconductor patterns, and
wherein the second surface of the source/drain pattern is closer to the power rail than an upper surface of the semiconductor pattern located farthest from the power rail among the semiconductor patterns.

### Claim 19 (depends on 15)

The device of claim 15,
wherein the source/drain pattern has a maximum width in the second direction at a level higher than the upper surface of the semiconductor pattern located closest to the power rail among the semiconductor patterns.