# US 12,183,740 B2 · Stacked field-effect transistors

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- Number: US 12,183,740 B2
- Document ID: US12183740B2
- Status: Granted
- Kind: B2
- Application number: 17/805,507
- Filed: 2022-06-06
- Published: 2023-12-07
- Granted: 2024-12-31
- Earliest claimed: 2022-06-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Kangguo Cheng; Curtis S. Durfee; Jay William Strane; Min Gyu Sung; Julien Frougier; Chanro Park
- Web page: https://patentgrep.com/patent/US12183740B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

## Claims

### Claim 1

A stacked field-effect transistor (FET) comprising:
a top device;
a bottom device; and
a transition region between the top device and the bottom device, the transition region comprising a plurality of inner spacers separated by a first distance and a first inter-layer dielectric (ILD) formed between each of the plurality of inner spacers,
wherein the top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers, the second channel sheet thickness being larger than both the first channel sheet thickness and the first distance.

### Claim 2 (depends on 1)

The stacked FET of claim 1, wherein the top and bottom devices are nanosheet transistors having the same doping type.

### Claim 3 (depends on 1)

The stacked FET of claim 1, wherein the top and bottom devices are nanosheet transistors having different doping types.

### Claim 4 (depends on 1)

The stacked FET of claim 1, wherein the top device comprises one or more top source/drain epitaxies and the bottom device comprises one or more bottom source/drain epitaxies.

### Claim 5 (depends on 4)

The stacked FET of claim 4, further comprising:
a second ILD formed on top of the top device;
a back-end-of-line (BEOL) formed on top of the second ILD;
a first contact connecting a first bottom source/drain epitaxy to the BEOL, wherein the first contact extends from the first bottom source/drain epitaxy through the first ILD, a first top source/drain epitaxy, and the second ILD.

### Claim 6 (depends on 5)

The stacked FET of claim 5, further comprising:
a second contact connecting a second top source/drain epitaxy to the BEOL, wherein the second contact extends from the second top source/drain epitaxy through the second ILD.

### Claim 7 (depends on 6)

The stacked FET of claim 6, further comprising:
a third ILD formed below the bottom device;
a backside interconnect formed below the third ILD; and
a third contact connecting a second bottom source/drain epitaxy to the backside interconnect, wherein the third contact extends from the second bottom source/drain epitaxy through the third ILD.

### Claim 8 (depends on 1)

The stacked FET of claim 1, wherein:
the second channel thickness is approximately 9 nm;
the first channel thickness is approximately 6 nm; and
the first distance is approximately 3 nm.

### Claim 9 (depends on 1)

The stacked FET of claim 1, wherein the top device is an nFET device and the bottom device is a pFET device.

### Claim 10

A method of fabricating a stacked FET, the method comprising:
forming a nanosheet stack on top of a substrate, wherein the nanosheet stack comprises a plurality of semiconductor layers separated by sacrificial layers, wherein the nanosheet stack comprises a top region, a middle region, and a bottom region, the semiconductor layers in the top region having a first thickness, the semiconductor layers in the middle region having a second thickness, and the semiconductor layers in the bottom region having a third thickness, wherein the second thickness is smaller than both the first and third thicknesses;
patterning the nanosheet stack to form a plurality of nanosheet fins;
indenting the sacrificial layers in between the nanosheet fins;
forming inner spacers in the indents in the sacrificial layers;
forming one or more bottom source/drain epitaxies between the nanosheet fins in the bottom region;
indenting the semiconductor layers in the middle region;
forming a bottom inter-layer dielectric (ILD) on the one or more bottom source/drain epitaxies, wherein the bottom ILD fills in the indents in the semiconductor layers;
forming one or more top source/drain epitaxies on top of the bottom ILD;
forming a top ILD on the one or more top source/drain epitaxies;
removing the sacrificial layers;
trimming the semiconductor layers such that the semiconductor layers in the middle region are removed and the semiconductor layers in the top and bottom regions are thinned; and
forming a metal gate around the semiconductor layers.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the nanosheet stack comprises:
forming a bottom nanosheet stack, wherein the bottom nanosheet stack comprises a first plurality of semiconductor layers separated by a sacrificial material, the first plurality of semiconductor layers having the first thickness;
forming a middle nanosheet stack on top of the bottom nanosheet stack, wherein the middle nanosheet stack comprises a second plurality of semiconductor layers separated by a sacrificial material, the second plurality of semiconductor layers having the second thickness;
forming a top nanosheet stack on top of the middle nanosheet stack, wherein the top nanosheet stack comprises a third plurality of semiconductor layers separated by a sacrificial material, the third plurality of semiconductor layers having the third thickness.

### Claim 12 (depends on 10)

The method of claim 10, wherein forming the one or more bottom source/drain epitaxies comprises:
filling the region between the nanosheet fins with an organic planarization layer (OPL);
recessing the OPL such that a top of the OPL is between the top semiconductor layer in the middle region and the bottom semiconductor layer in the top region;
forming a protective spacer along sidewalls of the semiconductor layers and the inner spacers in the top region, wherein the protective spacer is deposited along the sidewalls selective to the OPL;
removing the OPL; and
growing the bottom source/drain epitaxy to replace the OPL.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the one or more bottom source/drain epitaxies further comprises:
recessing the bottom source/drain epitaxy such that the top of the bottom source/drain epitaxy is between the top semiconductor layer in the bottom region and the bottom semiconductor layer in the middle region.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the one or more top source/drain epitaxies on top of the bottom ILD comprises:
removing the protective spacer; and
growing the top source/drain epitaxy on top of the bottom ILD.

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
forming a third ILD on top of the top ILD;
forming a first contact, the first contact extending from a first top source/drain epitaxy to a top of the third ILD;
forming a second contact, the first second extending from a first bottom source/drain epitaxy to the top of the third ILD; and
forming a back-end-of-line (BEOL) on top of the third ILD, the first contact, and the second contact.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first contact comprises:
forming a first trench in the third ILD and the top ILD, the first trench extending from the top of the third ILD to the top source/drain epitaxy, thereby exposing a portion of the top source/drain epitaxy; and
filling the first trench with a conductive material.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the second contact comprises:
forming a second trench, the second trench extending from the bottom source/drain epitaxy through the bottom ILD, through a second top source/drain epitaxy, through the top ILD, and through the third ILD, thereby exposing a portion of the bottom source/drain epitaxy; and
filling the second trench with a conductive material.

### Claim 18

A method comprising:
forming a top device comprising a first plurality of channel sheets separated by inner spacers and a metal gate;
forming a transition region comprising a plurality of inner spacers separated by a first distance and a first inter-layer dielectric (ILD) formed between each of the plurality of inner spacers; and
forming a bottom device comprising a second plurality of channel sheet separated by inner spacers and the metal gate,
wherein the top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between the inner spacers, the second channel sheet thickness being larger than both the first channel sheet thickness and the first distance.

### Claim 19 (depends on 18)

The method of claim 18, wherein the top and bottom devices are nanosheet transistors.

### Claim 20 (depends on 18)

The method of claim 18, wherein:
the second channel thickness is approximately 9 nm;
the first channel thickness is approximately 6 nm; and
the first distance is approximately 3 nm.