# US 12,183,739 B2 · Ribbon or wire transistor stack with selective dipole threshold voltage shifter

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- Number: US 12,183,739 B2
- Document ID: US12183739B2
- Status: Granted
- Kind: B2
- Application number: 17/127,280
- Filed: 2020-12-18
- Published: 2022-06-23
- Granted: 2024-12-31
- Earliest claimed: 2020-12-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Nicole Thomas; Eric Mattson; Sudarat Lee; Scott B. Clendenning; Tobias Brown-Heft; I-Cheng Tung; Thoe Michaelos; Gilbert Dewey; Charles Kuo; Matthew Metz; Marko Radosavljevic; Charles Mokhtarzadeh
- Web page: https://patentgrep.com/patent/US12183739B2

## CPC

- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

## Claims

### Claim 1

A transistor stack structure, comprising:
a first channel region over a second channel region, wherein the first and the second channel regions comprise at least one of Si or Ge;
a gate electrode around the first channel region, and around the second channel region;
a first gate insulator material between the gate electrode and each of the first channel region and the second channel region, wherein the first gate insulator material comprises oxygen and a first metal and encircles each of the first channel region and the second channel region;
a second gate insulator material in direct contact with the first channel region, and between the first channel region and the first gate insulator material encircling the first channel region; and
a third gate insulator material in direct contact with the second channel region, between the second channel region and the first gate insulator material encircling the second channel region, wherein:
both of the second and the third gate insulator materials comprise oxygen and the at least one of Si or Ge;
at least one of the second and third gate insulator materials comprise a second metal; and
an amount of the second metal varies between the second and third gate insulator materials.

### Claim 2 (depends on 1)

The transistor stack of claim 1, wherein the first metal is a first of Hf, Al, Zr, or Y, and wherein the second metal is Mg, Ca, Sr, La, Sc, Ba, Gd, Er, Yb, Lu, Ga, Mo, Co, Ni, Nb, or a second of Hf, Al, Zr, or Y.

### Claim 3 (depends on 1)

The transistor stack of claim 1, wherein:
the first channel region and the second channel region have substantially the same composition;
a first transistor comprises the first channel region and the first transistor has a first threshold voltage; and
a second transistor comprises the second channel material and the second transistor has a second threshold voltage, different than the first threshold voltage.

### Claim 4 (depends on 1)

The transistor stack of claim 1, wherein the second metal is present in both the second gate insulator material and the third gate insulator material.

### Claim 5 (depends on 1)

The transistor stack of claim 1, further comprising:
a first source material coupled to a first drain material through the first channel region, wherein the first source material and the first drain material are of a first conductivity type;
a second source material coupled to a second drain material through the second channel region, wherein the second source material and the second drain material are of a second conductivity type, complementary to the first conductivity type.

### Claim 6 (depends on 5)

The transistor stack of claim 5, wherein:
the first conductivity type is P-type, and the second conductivity type is N-type; and
the second metal is present in only one of the second gate insulator material or the third gate insulator material.

### Claim 7 (depends on 6)

The transistor stack of claim 6, wherein:
the second metal is Al, Ga, Mo, Co, Ni, or Nb and the amount of the second metal is greater in the second gate insulator material than in the third gate insulator material; or
the second metal is Mg, Ca, Sr, Ba, La, Sc, Y, Gd, Er, Yb, or Lu, and the amount of the second metal is greater in the third gate insulator material than in the second gate insulator material.

### Claim 8 (depends on 1)

The transistor stack of claim 1, further comprising a diffusion barrier, wherein the first gate insulator material is between the diffusion barrier and at least one of the first channel region or the second channel, and wherein the diffusion barrier comprises a third metal and nitrogen.

### Claim 9 (depends on 8)

The transistor stack of claim 8, wherein the third metal is Mo, Nb, Ti or W.

### Claim 10 (depends on 1)

The transistor stack of claim 1, further comprising a fourth gate insulator material around at least one of the first channel region or the second channel region, wherein the fourth gate insulator material comprises oxygen and the second metal.

### Claim 11 (depends on 10)

The transistor stack of claim 10, wherein the fourth gate insulator material is between the first gate insulator and the gate electrode.

### Claim 12 (depends on 11)

The transistor stack of claim 11, wherein the fourth gate insulator material is between the first gate insulator material and at least one of the second or third gate insulator materials.

### Claim 13 (depends on 1)

The transistor stack of claim 1, wherein the gate electrode comprises a work function metal around at least the first channel region and in physical contact with the first gate insulator material.

### Claim 14 (depends on 13)

The transistor stack of claim 13, wherein the gate electrode further comprises a second work function metal around the second channel region and in physical contact with the first gate insulator material.

### Claim 15

A computer system, comprising:
a power supply; and
an IC die coupled to the power supply, the IC die comprising an integrated circuit (IC) structure comprising a CMOS transistor stack, wherein the CMOS transistor stack comprises:
a first channel region of a first conductivity type over a second channel region of a second conductivity type, complementary to the first, wherein the first and the second channel regions comprise at least one of Si or Ge;
a gate electrode around the first channel region, and around the second channel region;
a first gate insulator material between the gate electrode and each of the first channel region and the second channel region, wherein the first gate insulator material comprises oxygen and a first metal and encircles each of the first channel region and the second channel region;
a second gate insulator material in direct contact with the first channel region, and between the first channel region and the first gate insulator material encircling the first channel region; and
a third gate insulator material in direct contact with the second channel region, and between the second channel region and the first gate insulator material encircling the second channel region, wherein:
both of the second and the third gate insulator materials comprise oxygen and the at least one of Si or Ge;
at least one of the second and third gate insulator materials comprise a second metal; and
an amount of the second metal varies between the second and third gate insulator materials.

### Claim 16 (depends on 15)

The computer system of claim 15, wherein the first conductivity type is P-type, and the second conductivity type is N-type; and wherein:
the second metal is Al, Ga, Mo, Co, Ni, or Nb, the second gate insulator material comprises the second metal, and the second metal is absent from the third gate insulator material; or
the second metal is Mg, Ca, Sr, Ba, La, Sc, Y, Gd, Er, Yb, or Lu, the third gate insulator material comprises the second metal, and the second metal is absent from the second gate insulator material.

### Claim 17 (depends on 15)

The computer system of claim 15, further comprising a battery coupled to the power supply.

### Claim 18

A transistor stack structure, comprising:
a first channel region over a second channel region, wherein the first and the second channel regions comprise at least one of Si or Ge;
a gate electrode around the first channel region, and around the second channel region;
a first source material coupled to a first drain material through the first channel region, wherein the first source material and the first drain material are of a first conductivity type;
a second source material coupled to a second drain material through the second channel region, wherein the second source material and the second drain material are of a second conductivity type, complementary to the first conductivity type;
a first gate insulator material between the gate electrode and each of the first channel region and the second channel region, wherein the first gate insulator material comprises oxygen and a first metal and encircles each of the first channel region and the second channel region;
a second gate insulator material in direct contact with the first channel region, and between the first channel region and the first gate insulator material encircling the first channel region, and in direct contact with the first channel region; and
a third gate insulator material in direct contact with the second channel region, between the second channel region and the first gate insulator material encircling the second channel region, wherein:
both of the second and the third gate insulator materials comprise oxygen and the at least one of Si or Ge;
at least one of the second and third gate insulator materials comprise a second metal; and
the second metal is Al, Ga, Mo, Co, Ni, or Nb and an amount of the second metal is greater in the second gate insulator material than in the third gate insulator where the first conductivity type is P-type, and the amount of the second metal is greater in the third gate insulator material than in the second gate insulator material where the first conductivity type is N-type, or the second metal is Mg, Ca, Sr, Ba, La, Sc, Y, Gd, Er, Yb, or Lu, and an amount of the second metal is greater in the second gate insulator material than in the third gate insulator where the first conductivity type is N-type, and the amount of the second metal is greater in the third gate insulator material than in the second gate insulator material where the first conductivity type is P-type.

### Claim 19 (depends on 18)

The transistor stack structure of claim 18, wherein:
the first conductivity type is P-type, and the second conductivity type is N-type;
the second metal is Al, Ga, Mo, Co, Ni, or Nb; and
the second metal is present in only the second gate insulator material.

### Claim 20 (depends on 18)

The transistor stack structure of claim 18, wherein:
the first conductivity type is P-type, and the second conductivity type is N-type;
the second metal is Mg, Ca, Sr, Ba, La, Sc, Y, Gd, Er, Yb, or Lu; and
the second metal is present in only the third gate insulator material.

### Claim 21 (depends on 18)

The transistor stack structure of claim 18, wherein:
the first conductivity type is N-type, and the second conductivity type is P-type;
the second metal is Al, Ga, Mo, Co, Ni, or Nb; and
the second metal is present in only the third gate insulator material.