# US 12,183,738 B2 · Cross-coupled gate design for stacked device with separated top-down gate

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- Number: US 12,183,738 B2
- Document ID: US12183738B2
- Status: Granted
- Kind: B2
- Application number: 17/221,355
- Filed: 2021-04-02
- Published: 2022-08-04
- Granted: 2024-12-31
- Earliest claimed: 2021-01-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Seunghyun Song; Seungyoung Lee; Saehan Park
- Web page: https://patentgrep.com/patent/US12183738B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10B 10/12: {comprising a MOSFET load element}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

## Claims

### Claim 1

A semiconductor device comprising:
a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors;
a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors;
a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors;
a first conductor connecting the first gate line to the fourth gate line;
a second conductor connecting the second gate line to the third gate line;
wherein the first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively,
wherein at least a portion of the first conductor extends vertically to connect the first gate line to the fourth gate line, and at least a portion of the second conductor extends vertically to connect the second gate line to the third gate line,
wherein the first conductor comprises:
at least one of a first contact formed on the first gate line and extending toward the second gate line in a horizontal direction, and a third contact formed on the fourth gate line and extending toward the third gate line in the horizontal direction; and
a first via connecting the first gate line to the fourth gate line in a vertical direction through the at least one of the first contact and the third contact, and
wherein the second conductor comprises:
at least one of a second contact formed on the second gate line and extending toward the first gate line in the horizontal direction, and a fourth contact formed on the third gate line and extending toward the fourth gate line in the horizontal direction; and
a second via connecting the second gate line to the third gate line in the vertical direction though the at least one of the second contact and the fourth contact.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of transistors comprise:
at least two n-type metal oxide semiconductor (NMOS) transistors and at least two p-type metal oxide semiconductor (PMOS) transistors,
wherein the first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first channel layer passing through the first gate line and the second gate line; and
a second channel layer passing through the third gate line and the fourth gate line.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first gate line, the second gate line, the third gate line and the fourth gate line extend in a first direction, and
wherein the first channel layer and the second channel layer extend in a second direction perpendicular to the first direction.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first gate line and the fourth gate line have a substantially equal length in another horizontal direction perpendicular to the horizontal direction in which the at least one of the first contact and the third contact is extended.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the second gate line and the third gate line have a substantially equal length in the other horizontal direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first gate line and the third gate line are vertically overlapping each other, and the second gate line and the fourth gate line are vertically overlapping each other.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first gate line has a smaller length than the third gate line in another horizontal direction perpendicular to the horizontal direction in which the at least one of the first contact and the third contact is extended, and
wherein the second gate line has a smaller length than the fourth gate line in the other horizontal direction.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first conductor comprises the first contact, among the first contact and the third contact, and the first via, and
wherein the second conductor comprises the second contact, among the second contact and the fourth contact, and the second via,
wherein the first via connects the first contact on the first gate line to the fourth gate line in the vertical direction, and
wherein the second via connects the second contact on the second gate line to the third gate line in the vertical direction.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first via and the second via are located between the first gate line and the second gate line.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first via and the second via are located opposite from each other with respect to a channel layer disposed therebetween.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the first contact is connected to the first gate line, the third contact is connected to the fourth gate line, and the first via connects the first contact to the third contact in the vertical direction, and
wherein the second contact is connected to the second gate line, the fourth contact is connected to the third gate line, and the second via connects the second contact to the fourth contact in the vertical direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first contact is connected to a top surface of the first gate line and the third contact is connected to a bottom surface of the fourth gate line, and
wherein the second contact is connected to a top surface of the second gate line and the fourth contact is connected to a bottom surface of the third gate line.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the first contact is connected to a side surface of the first gate line and the third contact is connected to a side surface of the fourth gate line, and
wherein the second contact is connected to a side surface of the second gate line and the fourth contact is connected to a side surface of the third gate line.