# US 12,183,736 B2 · Backside PN junction diode

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- Number: US 12,183,736 B2
- Document ID: US12183736B2
- Status: Granted
- Kind: B2
- Application number: 18/356,802
- Filed: 2023-07-21
- Published: 2023-11-09
- Granted: 2024-12-31
- Earliest claimed: 2020-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Xuan Huang; Ching-Wei Tsai; Jam-Wem Lee; Kuo-Ji Chen; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US12183736B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/221: {of only diodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a backside dielectric layer;
a backside conductive feature disposed in the backside dielectric layer and extending lengthwise along a first direction;
an isolation feature disposed over the backside dielectric layer;
a silicide layer disposed on the backside conductive feature;
an epitaxial layer disposed on the silicide layer;
a semiconductor feature disposed on the epitaxial layer; and
a first source/drain feature disposed on the semiconductor feature.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a second source/drain feature disposed on the semiconductor feature; and
a plurality of channel members extending between the first source/drain feature and the second source/drain feature along the first direction.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the first source/drain feature and the second source/drain feature are electrically coupled together.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2,
wherein the semiconductor feature comprises a first type dopant,
wherein the first source/drain feature and the second source/drain feature comprise a second type dopant different from the first type dopant,
wherein the epitaxial layer comprises the first type dopant.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein a concentration of the first type dopant in the epitaxial layer is greater than a concentration of the first type dopant in the first source/drain feature and the second source/drain feature.

### Claim 6 (depends on 2)

The semiconductor structure of claim 2, further comprising:
a gate structure wrapping around each of the plurality of channel members.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the gate structure is electrically floating.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the gate structure is spaced apart from the first source/drain feature and the second source/drain feature by a plurality of inner spacer features.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the silicide layer, the epitaxial layer, and the semiconductor feature are sandwiched between a first portion of the isolation feature and a second portion of the isolation feature along a second direction perpendicular to the first direction.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the silicide layer comprises titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN).

### Claim 11

A semiconductor structure, comprising:
a backside conductive feature extending lengthwise along a first direction;
a silicide layer disposed on the backside conductive feature and extending along the first direction;
an epitaxial layer disposed on the silicide layer and extending along the first direction;
a semiconductor feature disposed on the epitaxial layer and extending along the first direction;
a first source/drain feature and a second source/drain feature disposed over the semiconductor feature;
a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature along the first direction; and
a gate structure wrapping around each of the plurality of nanostructures,
wherein the first source/drain feature is electrically coupled to the backside conductive feature.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the gate structure is electrically floating.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11,
wherein the first source/drain feature and the semiconductor feature are doped with a first type dopant,
wherein the second source/drain feature is doped with a second type dopant different from the first type dopant.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11, wherein the silicide layer, the epitaxial layer, and the semiconductor feature are sandwiched between a first portion and a second portion of an isolation feature along a second direction perpendicular to the first direction.

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein the silicide layer comprises a thickness between about 3 nm and about 5 nm.

### Claim 16

A device, comprising:
a first PN junction diode comprising:
a well region doped with a dopant of a first conductivity type,
a first epitaxial feature disposed over the well region, the first epitaxial feature being doped with a dopant of a second conductivity type different from the first conductivity type,
a first contact disposed on and in contact with the first epitaxial feature, and
a backside conductive feature disposed below the well region; and
a second PN junction diode comprising:
a second epitaxial feature disposed over the well region and spaced apart from the first epitaxial feature, the second epitaxial feature being doped with the dopant of the first conductivity type,
a plurality of nanostructures extending between the first epitaxial feature and the second epitaxial feature along a first directions, and
the first epitaxial feature.

### Claim 17 (depends on 16)

The device of claim 16, further comprising:
a gate structure wrapping around each of the plurality of nanostructures,
wherein the gate structure is electrically floating.

### Claim 18 (depends on 17)

The device of claim 17, wherein the gate structure is spaced apart from the first epitaxial feature and the second epitaxial feature by a plurality of inner spacer features.

### Claim 19 (depends on 16)

The device of claim 16, further comprising:
a silicide layer disposed on the backside conductive feature; and
an epitaxial layer disposed on the silicide layer,
wherein the silicide layer and the epitaxial layer are sandwiched between the well region and the backside conductive feature.

### Claim 20 (depends on 19)

The device of claim 19, wherein the silicide layer comprises titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), or titanium silicon nitride (TiSiN).