# US 12,183,733 B2 · Semiconductor device structure and methods of forming the same

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- Number: US 12,183,733 B2
- Document ID: US12183733B2
- Status: Granted
- Kind: B2
- Application number: 18/225,139
- Filed: 2023-07-23
- Published: 2023-11-16
- Granted: 2024-12-31
- Earliest claimed: 2020-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jia-Chuan You; Shi-Ning Ju; Kuo-Cheng Chiang; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12183733B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/43: Layouts of interconnections
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0153: {using gate cut processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

## Claims

### Claim 1

A method, comprising:
forming first and second fins from a substrate;
forming a dielectric feature between the first and second fins;
forming a gate electrode layer over the substrate adjacent the dielectric feature;
forming a seed layer on the gate electrode layer and the dielectric feature;
forming a conductive layer on the seed layer;
forming an opening in the seed layer and the conductive layer to expose the dielectric feature; and
forming a first dielectric material in the opening on the dielectric feature.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the dielectric feature comprises:
forming a liner between the first and second fins;
forming a second dielectric material on the liner; and
forming a third dielectric material on the liner and the second dielectric material.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming interlayer dielectric layers over the substrate, wherein the interlayer dielectric layers define a trench, and the seed layer and the conductive layer are formed on a bottom of the trench.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the seed layer comprises:
forming a blanket layer over the interlayer dielectric layers, adjacent spacers in the trench, and on the bottom of the trench;
removing portions of the blanket layer formed adjacent the spacers in the trench; and
removing portions of the blanket layer formed over the interlayer dielectric layers.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the seed layer further comprises:
forming a mask on the blanket layer after removing portions of the blanket layer formed adjacent the spacers in the trench;
removing portions of the mask over the interlayer dielectric layers by a first etch process to expose the portions of the blanket layer disposed over the interlayer dielectric layers; and
removing the exposed portions of the blanket layer by a second etch process.

### Claim 6 (depends on 4)

The method of claim 4, wherein the forming the seed layer further comprises:
forming a mask on the blanket layer after removing portions of the blanket layer formed adjacent the spacers in the trench;
removing portions of the mask and blanket layer over the interlayer dielectric layers by a planarization process.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the first dielectric material in the first opening comprises forming the first dielectric material on the conductive layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming a second opening in the first dielectric material, the conductive layer, and the seed layer; and
forming a conductive feature in the second opening on the gate electrode layer.

### Claim 9

A method for forming a semiconductor device structure, comprising:
forming a gate electrode layer over a substrate;
recessing the gate electrode layer, wherein the gate electrode layer is located at a bottom of a trench, and the trench is formed between two interlayer dielectric (ILD) layers;
forming a seed layer on the gate electrode layer, over the two ILD layers and adjacent the two ILD layers, wherein a portion of the seed layer formed on the gate electrode layer has a first thickness, and a portion of the seed layer formed adjacent the two ILD layers has a second thickness substantially less than the first thickness;
removing the portion of the seed layer formed adjacent the two ILD layers;
forming a mask on the portions of the seed layer formed on the gate electrode layer and over the two ILD layers;
removing a portion of the mask to expose the portion of the seed layer formed over the two ILD layers;
removing the exposed portion of the seed layer;
removing the mask; and
forming a conductive layer on the seed layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising a contact etch stop layer formed on the two ILD layers.

### Claim 11 (depends on 10)

The method of claim 10, further comprising spacers disposed adjacent and in contact with the contact etch stop layer, wherein the portion of the seed layer disposed adjacent the two ILD layers is in contact with the spacers.

### Claim 12 (depends on 11)

The method of claim 11, further comprising a nitrogen-containing layer disposed on each of the two ILD layers, wherein the portion of the seed layer disposed over the two ILD layers is disposed on the nitrogen-containing layer.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming an opening in the conductive layer and the seed layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the opening is formed by a first etch process to remove a portion of the conductive layer and a second etch process to remove a portion of the seed layer.

### Claim 15

A method for forming a semiconductor device structure, comprising:
forming a first gate electrode layer over a dielectric feature;
recessing the first gate electrode layer to form second and third gate electrode layers, wherein top surfaces of the second and third gate electrode layers and a top surface of the dielectric feature are substantially coplanar;
depositing a seed layer, wherein the seed layer comprises a bottom portion disposed on the second gate electrode layer, the third gate electrode layer, and the dielectric feature and vertical portions extending upward from the bottom portion;
removing the vertical portions of the seed layer; and
selectively depositing a conductive layer on the seed layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising performing a first etch process to form an opening in the conductive layer, wherein a portion of the seed layer is exposed in the opening.

### Claim 17 (depends on 16)

The method of claim 16, further comprising performing a second etch process to remove the exposed portion of the seed layer and to expose the dielectric feature.

### Claim 18 (depends on 17)

The method of claim 17, further comprising depositing a dielectric material in the opening and on the conductive layer, wherein the dielectric material is in contact with the dielectric feature.

### Claim 19 (depends on 18)

The method of claim 18, wherein the seed layer and the conductive layer are deposited in a trench, and the dielectric material fills the trench.

### Claim 20 (depends on 19)

The method of claim 19, wherein the trench is formed between two interlayer dielectric layers.