# US 12,183,732 B2 · Semiconductor devices including an isolation insulating pattern on a boundary region of a substrate and between first active patterns and second active patterns

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- Number: US 12,183,732 B2
- Document ID: US12183732B2
- Status: Granted
- Kind: B2
- Application number: 18/326,522
- Filed: 2023-05-31
- Published: 2023-09-28
- Granted: 2024-12-31
- Earliest claimed: 2020-12-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Inwon Park; Bosoon Kim; Jongsoon Park
- Web page: https://patentgrep.com/patent/US12183732B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0128: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including a first region, a second region, and a boundary region between the first region and the second region;
first active patterns on the first region of the substrate and spaced apart from each other in a first direction parallel to a bottom surface of the substrate;
second active patterns on the second region of the substrate and spaced apart from each other in the first direction; and
an isolation insulating pattern on the boundary region of the substrate, the isolation insulating pattern between the first active patterns and the second active patterns, wherein
the isolation insulating pattern is between a corresponding first active pattern of the first active patterns and a corresponding second active pattern of the second active patterns, and
a bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to the corresponding first active pattern, a second bottom surface adjacent to the corresponding second active pattern, and a protrusion surface protruding from the first bottom surface and the second bottom surface toward an inside of the isolation insulating pattern, wherein
the protrusion surface includes a first sidewall and a second sidewall,
the first sidewall protrudes from the first bottom surface toward to the inside of the isolation insulating pattern,
the second sidewall protrudes from the second bottom surface toward the inside of the isolation insulating pattern, and
a horizontal distance between the first sidewall and the second sidewall decreases as a vertical level of the protrusion surface increases.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein
the first active patterns and the second active patterns extend long in a second direction,
the second direction is parallel to the bottom surface of the substrate and intersects the first direction,
the isolation insulating pattern extends long in the second direction between the corresponding first active pattern and the corresponding second active pattern, and
the protrusion surface extends long in the second direction.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein
each of the first active patterns and the second active patterns has a width in the first direction, at least some of the first active patterns have different widths, and the second active patterns have equal widths.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
first device isolation patterns between the first active patterns,
wherein the protrusion surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the first device isolation patterns with respect to the bottom surface of the substrate.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, further comprising:
second device isolation patterns between the second active patterns,
wherein the protrusion surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the second device isolation patterns with respect to the bottom surface of the substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
first channel patterns on the first active patterns, respectively,
wherein each of the first channel patterns includes a plurality of first semiconductor patterns vertically spaced apart from each other on each of the first active patterns.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising:
second channel patterns on the second active patterns, respectively,
wherein each of the second channel patterns includes a plurality of second semiconductor patterns vertically spaced apart from each other on each of the second active patterns.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein
a first sidewall of the isolation insulating pattern is in contact with the corresponding first active pattern,
a second sidewall of the isolation insulating pattern is in contact with the corresponding second active pattern,
the bottom surface of the isolation insulating pattern is in contact with the substrate between the first sidewall and the second sidewall.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein
each of the first active patterns and the second active patterns has a width in the first direction, and
widths of the second active patterns are less than widths of at least some of the first active patterns.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising;
first device isolation patterns between the first active patterns; and
second device isolation patterns between the second active patterns,
wherein each of the first device isolation patterns has a first width in the first direction, each of the second device isolation patterns has a second width in the first direction, and the isolation insulating pattern has a third width in the first direction,
wherein the third width is greater than the first width and the second width.

### Claim 11

A semiconductor device comprising:
a substrate including a first region, a second region, and a boundary region between the first region and the second region;
first active patterns on the first region of the substrate;
second active patterns on the second region of the substrate; and
an isolation insulating pattern on the boundary region of the substrate, the isolation insulating pattern between the first active patterns and the second active patterns, wherein
the isolation insulating pattern is between a corresponding first active pattern of the first active patterns and a corresponding second active pattern of the second active patterns,
a bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to the corresponding first active pattern, a second bottom surface adjacent to the corresponding second active pattern, and a protrusion surface between the first bottom surface and the second bottom surface,
the protrusion surface includes a third bottom surface is located at a higher height than the first bottom surface and the second bottom surface with respect to a bottom surface of the substrate,
the protrusion surface of the isolation insulating pattern is closer to a sidewall of the corresponding second active pattern than to a sidewall of the corresponding first active pattern.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein
the first active patterns and the second active patterns are spaced apart from each other in a first direction parallel to the bottom surface of the substrate and extend long in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction,
each of the first active patterns and the second active patterns has a width in the first direction, and
a width of at least one of the first active patterns is different from a width of an other of the first active patterns.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein
widths of the second active patterns are equal to each other.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein widths of the second active patterns are less than widths of at least some of the first active patterns.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, further comprising:
first device isolation patterns between the first active patterns; and
second device isolation patterns between the second active patterns,
wherein each of the first device isolation patterns has a first width in the first direction, each of the second device isolation patterns has a second width in the first direction, and the isolation insulating pattern has a third width in the first direction,
wherein the third width is greater than the first width and the second width.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the isolation insulating pattern extends long in the second direction between the corresponding first active pattern and the corresponding second active pattern, and
wherein the first bottom surface, the second bottom surface, and the protrusion surface of the isolation insulating pattern extend long in the second direction.

### Claim 17 (depends on 11)

The semiconductor device of claim 11, further comprising:
first device isolation patterns between the first active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the first device isolation patterns with respect to the bottom surface of the substrate.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
second device isolation patterns between the second active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the second device isolation patterns with respect to the bottom surface of the substrate.

### Claim 19 (depends on 11)

The semiconductor device of claim 11, further comprising:
first channel patterns on the first active patterns, respectively; and
second channel patterns on the second active patterns, respectively,
wherein each of the first channel patterns includes a plurality of first semiconductor patterns vertically spaced apart from each other on each of the first active patterns.