# US 12,183,731 B2 · Dummy device for core device to operate in a safe operating area and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,731 B2 - Document ID: US12183731B2 - Status: Granted - Kind: B2 - Application number: 17/235,822 - Filed: 2021-04-20 - Published: 2022-07-21 - Granted: 2024-12-31 - Earliest claimed: 2021-01-18 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Szu-Chun Tsao; Jaw-Juinn Horng - Web page: https://patentgrep.com/patent/US12183731B2 ## CPC - H03K 17/08104: {in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence)} - H10D 84/83: of only insulated-gate FETs [IGFET] - H03K 17/04106: {in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence)} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 89/10: Integrated device layouts - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor. ## Claims ### Claim 1 A semiconductor device for enabling a core devices to operate in a safe operating area, comprising: a core transistor of the core device having a drain configured to receive a first voltage; a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor, wherein a gate and a source of the first dummy transistor are connected to each other, a drain of the second dummy transistor is connected to the source of the first dummy transistor, and a gate of the second dummy transistor is connected to the drain of the core transistor; and a second dummy device connected between the first dummy device and the core transistor, wherein the second dummy device comprises a third dummy transistor, and wherein a gate, a source and a drain of the third dummy transistor are connected together. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a source of the second dummy transistor is configured to receive a first reference voltage. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein a gate of the core transistor is configured to receive a second reference voltage. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the first reference voltage is identical to the second reference voltage. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein a difference between the first voltage and the first reference voltage is less than a safe operating area limit of the core transistor. ### Claim 6 (depends on 2) The semiconductor device of claim 2, wherein the first reference voltage is less than a safe operating area limit of the core transistor. ### Claim 7 A semiconductor device for enabling a core devices to operate in a safe operating area, comprising: a substrate; a continuous active region on the substrate; a core transistor of the core device having a drain configured to receive a first voltage; a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor, wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor, and a source of the second dummy transistor is disposed adjacent to an edge of the continuous active region; and a second dummy device connected between the first dummy device and the core transistor, wherein the second dummy device comprises a third dummy transistor, and wherein a gate, a source and a drain of the third dummy transistor are connected together. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein a gate and a source of the first dummy transistor are connected to each other. ### Claim 9 (depends on 7) The semiconductor device of claim 7, wherein the source of the second dummy transistor is configured to receive a first reference voltage. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a gate of the core transistor is configured to receive a second reference voltage. ### Claim 11 (depends on 7) The semiconductor device of claim 7, wherein the first dummy transistor has a first threshold voltage and the second dummy transistor has a second threshold voltage, and wherein the first threshold voltage is different than the second threshold voltage. ### Claim 12 (depends on 7) The semiconductor device of claim 7, wherein the first voltage is an input/output (IO) voltage greater than approximately 1.2 volts (V). ### Claim 13 (depends on 9) The semiconductor device of claim 9, wherein a difference between the first voltage and the first reference voltage is less than a safe operating area limit of the core transistor. ### Claim 14 A semiconductor device for enabling a core devices to operate in a safe operating area, comprising: a core transistor of the core device having a drain configured to receive a first voltage; a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor, wherein a drain of the first dummy transistor is coupled to the drain of the core transistor, a gate and a source of the first dummy transistor are connected to each other, a drain of the second dummy transistor is connected to the source of the first dummy transistor, and a gate and a source of the second dummy transistor are connected to each other; and a second dummy device connected between the first dummy device and the core transistor, wherein the second dummy device comprises a third dummy transistor, and wherein a gate, a source and a drain of the third dummy transistor are connected together. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein a source of the second dummy transistor is configured to receive a first reference voltage. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein a gate of the core transistor is configured to receive a second reference voltage. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the first reference voltage is identical to the second reference voltage. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein a difference between the first voltage and the first reference voltage is less than a safe operating area limit of the core transistor. ### Claim 19 (depends on 10) The semiconductor device of claim 10, wherein the first reference voltage is identical to the second reference voltage. ### Claim 20 (depends on 15) The semiconductor device of claim 15, wherein the first reference voltage is less than a safe operating area limit of the core transistor.