# US 12,183,729 B2 · Integrated circuit filler and method thereof

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- Number: US 12,183,729 B2
- Document ID: US12183729B2
- Status: Granted
- Kind: B2
- Application number: 18/357,224
- Filed: 2023-07-24
- Published: 2023-11-16
- Granted: 2024-12-31
- Earliest claimed: 2016-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tseng Chin Lo; Molly Chang; Ya-Wen Tseng; Chih-Ting Sun; Zi-Kuan Li; Bo-Sen Chang; Geng-He Lin
- Web page: https://patentgrep.com/patent/US12183729B2

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/27: {Structural arrangements therefor}
- H10P 76/2041: {Photolithographic processes}
- H10P 74/20: characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

## Claims

### Claim 1

A method, comprising:
receiving an integrated circuit (IC) layout design including a pre-designed filler cell having a first layout pattern corresponding to a first failure mode;
fabricating a first mask associated with a first substrate layer, the first mask including the first layout pattern;
patterning, using the first mask, the first substrate layer to provide a patterned first substrate layer including the first layout pattern; and
inspecting the patterned first substrate layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first substrate layer includes a metal layer, an oxide layer, or a semiconductor layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the IC layout design further includes a standard filler cell and a plurality of functional cells, and wherein the pre-designed filler cell and the standard filler cell are disposed within a gap among the plurality of functional cells.

### Claim 4 (depends on 1)

The method of claim 1, wherein the IC layout design includes another pre-designed filler cell having a second layout pattern corresponding to a second failure mode.

### Claim 5 (depends on 1)

The method of claim 1, wherein the pre-designed filler cell includes a systematic design of experiments (DOE) based on the first failure mode.

### Claim 6 (depends on 4)

The method of claim 4, wherein the another pre-designed filler cell includes a systematic design of experiments (DOE) based on the second failure mode.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
fabricating a second mask associated with a second substrate layer, the second mask including the first layout pattern.

### Claim 8 (depends on 4)

The method of claim 4, further comprising:
fabricating a second mask associated with a second substrate layer, the second mask including the second layout pattern.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
patterning, using the second mask, the second substrate layer to provide a patterned second substrate layer including the first layout pattern; and
inspecting the patterned second substrate layer.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
patterning, using the second mask, the second substrate layer to provide a patterned second substrate layer including the second layout pattern; and
inspecting the patterned second substrate layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the inspecting the patterned first substrate layer is performed using an electron beam (e-beam) inspection process.

### Claim 12

A method, comprising:
fabricating a plurality of masks based on an integrated circuit (IC) layout design, wherein at least one of the plurality of masks includes a redesigned filler cell associated with a particular failure mode; and
patterning and inspecting each of a plurality of substrate layers, wherein the patterning of at least one of the plurality of substrate layers transfers a layout pattern of the redesigned filler cell, using the at least one of the plurality of masks, onto the at least one of the plurality of substrate layers, and wherein the inspection of the at least one of the plurality of substrate layer includes inspection of the redesigned filler cell patterned onto the at least one of the plurality of substrate layers.

### Claim 13 (depends on 12)

The method of claim 12, wherein a first one of the plurality of masks includes a first redesigned filler cell associated with a first failure mode, and wherein a second one of the plurality of masks includes a second redesigned filler cell associated with a second failure mode.

### Claim 14 (depends on 13)

The method of claim 13, wherein the patterning of a first one of the plurality of substrate layers transfers a first layout pattern of the first redesigned filler cell, using the first one of the plurality of masks, onto the first one of the plurality of substrate layers, and wherein the patterning of a second one of the plurality of substrate layers transfers a second layout pattern of the second redesigned filler cell, using the second one of the plurality of masks, onto the second one of the plurality of substrate layers.

### Claim 15 (depends on 13)

The method of claim 13, wherein the inspection of a first one of the plurality of substrate layers includes inspection of the first redesigned filler cell patterned onto the first one of the plurality of substrate layers, and wherein the inspection of a second one of the plurality of substrate layers includes inspection of the second redesigned filler cell patterned onto the second one of the plurality of substrate layers.

### Claim 16 (depends on 12)

The method of claim 12, wherein the IC layout design further includes a standard filler cell and a plurality of functional cells, and wherein the redesigned filler cell and the standard filler cell are disposed within a gap among the plurality of functional cells.

### Claim 17

A method, comprising:
fabricating a mask having a layout pattern associated with a particular layer of an integrated circuit (IC), wherein the layout pattern includes a first portion associated with a first logic cell and a second portion adjacent to the first portion, the second portion of the layout pattern associated with a first failure mode corresponding to the first portion of the layout pattern;
patterning, using the mask, a substrate to include the layout pattern associated with the particular layer of the IC; and
inspecting the patterned substrate.

### Claim 18 (depends on 17)

The method of claim 17, wherein the layout pattern further includes a third portion adjacent to the first and second portions, and wherein the third portion of the layout pattern is associated with a standard filler cell.

### Claim 19 (depends on 17)

The method of claim 17, wherein the layout pattern further includes a third portion adjacent to the first and second portions, and wherein the third portion of the layout pattern is associated with a second failure mode corresponding to a fourth portion of the layout pattern adjacent to the third portion, the fourth portion associated with a second logic cell.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second failure mode is different than, or the same as, the first failure mode.