# US 12,183,728 B2 · Process control for package formation

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- Number: US 12,183,728 B2
- Document ID: US12183728B2
- Status: Granted
- Kind: B2
- Application number: 18/149,472
- Filed: 2023-01-03
- Published: 2023-05-11
- Granted: 2024-12-31
- Earliest claimed: 2017-11-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ming-Fa Chen; Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US12183728B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/655: Fan-out layouts
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

## Claims

### Claim 1

A package comprising:
a first device die;
an isolation region over the first device die, wherein the first device die comprises portions laterally beyond outmost edges of the isolation region, and wherein the isolation region comprises:
a first etch stop layer over the first device die;
a first dielectric layer over the first etch stop layer;
a second etch stop layer over the first dielectric layer; and
a second dielectric layer over the second etch stop layer; and
a through-via penetrating through the isolation region to electrically connect to the first device die.

### Claim 2 (depends on 1)

The package of claim 1, wherein the first etch stop layer physically contacts a top surface of the first device die, and the first dielectric layer directly contacts the first etch stop layer and the second etch stop layer.

### Claim 3 (depends on 1)

The package of claim 1, wherein the first etch stop layer has a U-shape in a cross-sectional view of the package, and the first dielectric layer, the second etch stop layer, and the second dielectric layer are in the U-shape.

### Claim 4 (depends on 1)

The package of claim 1, wherein the through-via is tapered with upper portions being increasingly wider than respective lower portions.

### Claim 5 (depends on 1)

The package of claim 1, wherein the first etch stop layer has a first thickness smaller than a second thickness of the second etch stop layer.

### Claim 6 (depends on 1)

The package of claim 1, wherein the first etch stop layer and the second etch stop layer are formed of a first dielectric material, and the first dielectric layer and the second dielectric layer are formed of a second dielectric material different from the first dielectric material.

### Claim 7 (depends on 1)

The package of claim 1, wherein each of the first etch stop layer, the first dielectric layer, and the second etch stop layer is a conformal layer.

### Claim 8 (depends on 1)

The package of claim 1 further comprising:
a second device die over and bonding to the first device die; and
a third device die over and bonding to the first device die, wherein the isolation region is between, and is in contact with, the first device die and the second device die.

### Claim 9 (depends on 8)

The package of claim 8, wherein the first etch stop layer comprises:
a first sidewall contacting the first device die; and
a second sidewall contacting the second device die.

### Claim 10

A package comprising:
a first package component;
a dielectric isolation region over and contacting the first package component, wherein the dielectric isolation region comprises:
a first plurality of layers formed of a first material; and
a second plurality of layers formed of a second material different from the first material, wherein each of the second plurality of layers overlaps, and is in physical contact with, a corresponding one of the first plurality of layers;
a second package component over and bonding to the first package component; and
a dielectric layer over and bonding to top surfaces of both of the second package component and the dielectric isolation region.

### Claim 11 (depends on 10)

The package of claim 10 further comprising a third package component over and bonding to the first package component, wherein the dielectric isolation region is between, and contacts sidewalls of, the second package component and the third package component.

### Claim 12 (depends on 10)

The package of claim 10, wherein a bottom layer in the first plurality of layers comprises:
a horizontal portion in physical contact with a top surface of the first package component; and
a vertical portion in physical contact with a sidewall of the second package component.

### Claim 13 (depends on 10)

The package of claim 10, wherein the first plurality of layers comprise silicon nitride, and the second plurality of layers comprise silicon oxide.

### Claim 14 (depends on 10)

The package of claim 10, wherein each of the first plurality of layers is conformal, and wherein at least a bottom layer among the second plurality of layers is conformal.

### Claim 15 (depends on 10)

The package of claim 10 further comprising a through-via penetrating through the first plurality of layers and the second plurality of layers to electrically connect to the first package component, wherein the through-via is in contact with each of the first plurality of layers and the second plurality of layers.

### Claim 16 (depends on 15)

The package of claim 15, wherein the through-via is tapered, with upper portions of the through-via being wider than respective lower portions of the through-via.

### Claim 17

A package comprising:
a first package component, wherein the first package component comprises an electrical connector;
a dielectric isolation region over and in physical contact with the first package component, wherein the dielectric isolation region comprises:
a first dielectric layer;
a second dielectric layer over the first dielectric layer; and
a third dielectric layer over the second dielectric layer, wherein the first dielectric layer comprises a first dielectric material, the second dielectric layer comprises a second dielectric material different from the first dielectric material, and the third dielectric layer comprises a third dielectric material different from the second dielectric material; and
a conductive feature penetrating through the dielectric isolation region to electrically connect to the electrical connector of the first package component; and
a second package component over and joined to the first package component, wherein the dielectric isolation region comprises a first sidewall contacting the second package component.

### Claim 18 (depends on 17)

The package of claim 17 further comprising a third package component over and joined to the first package component, wherein the dielectric isolation region further comprises a second sidewall contacting the third package component.

### Claim 19 (depends on 17)

The package of claim 17, wherein the dielectric isolation region further comprises a dielectric region between opposing portions of the third dielectric layer.

### Claim 20 (depends on 1)

The package of claim 1, wherein cross-sections of the first etch stop layer and the second etch stop layer have U-shapes.