# US 12,183,718 B2 · Semiconductor package having a high reliability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,718 B2 - Document ID: US12183718B2 - Status: Granted - Kind: B2 - Application number: 18/409,778 - Filed: 2024-01-10 - Published: 2024-05-02 - Granted: 2024-12-31 - Earliest claimed: 2016-02-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ji-Hwan Hwang; Sang-Sick Park; Tae-Hong Min; Geol Nam - Web page: https://patentgrep.com/patent/US12183718B2 ## CPC - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/072: {of bump connectors} - H10W 72/07252: {changes in structures or sizes} - H10W 72/073: {of die-attach connectors} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/20: Configurations of stacked chips - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween. ## Claims ### Claim 1 A method of fabricating a semiconductor package, the method comprising: providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals; stacking the plurality of semiconductor devices on the package substrate at a first temperature, each for a first time; heating the plurality of semiconductor devices to a second temperature higher than the first temperature; maintaining the plurality of semiconductor devices at the second temperature for a second time greater than the first time while applying pressure to the plurality of semiconductor devices, so that the connection terminals are reflowed and the plurality of semiconductor devices are bonded to the package substrate; and molding the plurality of semiconductor devices. ### Claim 2 (depends on 1) The method of claim 1, wherein the heating of the plurality of semiconductor devices to a second temperature is performed after the stacking of the plurality of semiconductor devices. ### Claim 3 (depends on 1) The method of claim 1, wherein each of the plurality semiconductor devices have a pre-applied underfill film on a surface. ### Claim 4 (depends on 3) The method of claim 3, wherein the plurality of semiconductor devices are coupled with each other depending on viscosity of the pre-applied underfill film during the stacking of the plurality of semiconductor devices. ### Claim 5 (depends on 3) The method of claim 3, wherein during the maintaining the plurality of semiconductor devices at the second temperature for the second time, the pre-applied underfill film is reflowed to form a plurality of underfill fillets, in which at least two neighboring underfill fillets form one continuous structure without an interface therebetween. ### Claim 6 (depends on 5) The method of claim 5, wherein the pre-applied underfill films are reflowed and form a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. ### Claim 7 (depends on 6) The method of claim 6, wherein the at least two neighboring underfill fillets form one continuous structure by a flowing together of corresponding protrusions thereof. ### Claim 8 (depends on 5) The method of claim 5, further comprising curing the plurality of underfill fillets by cooling the plurality of semiconductor devices, after heating the plurality of semiconductor devices to a second temperature higher than the first temperature. ### Claim 9 (depends on 8) The method of claim 8, wherein the cooling of the plurality of semiconductor devices is not performed before heating the plurality of semiconductor devices to the second temperature higher than the first temperature. ### Claim 10 (depends on 8) The method of claim 8, wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate after the curing. ### Claim 11 (depends on 1) The method of claim 1, wherein the first temperature ranges from about 80° C. to about 100° C. ### Claim 12 (depends on 1) The method of claim 1, wherein the second temperature ranges from about 220° C. to about 280° C. ### Claim 13 A method of fabricating a semiconductor package, the method comprising: providing a package substrate, a first semiconductor device, and a second semiconductor device, the first semiconductor device having a first plurality of connection terminals and the second semiconductor device having a second plurality of connection terminals; horizontally stacking the first semiconductor device and the second semiconductor device sequentially on the package substrate at a first temperature, each for a first time, to form a stack structure; simultaneously reflowing the stack structure at a second temperature higher than the first temperature for a second time greater than the first time so that the first semiconductor device and the second semiconductor device are bonded to the package substrate. ### Claim 14 (depends on 13) The method of claim 13, wherein at least one of the first semiconductor device and the second semiconductor device is a sub-package and the semiconductor package is a package-on-package (PoP) type of package. ### Claim 15 (depends on 13) The method of claim 13, further comprising curing the stack structure by cooling after the reflowing. ### Claim 16 (depends on 13) The method of claim 13, wherein the first semiconductor device having a first pre-applied underfill film and the second semiconductor device having a second pre-applied underfill film, after the reflowing the stack structure, the first pre-applied underfill film and the second pre-applied underfill film form one continuous structure without an interface therebetween. ### Claim 17 (depends on 15) The method of claim 15, further comprising molding the first semiconductor device and the second semiconductor device with molding resin. ### Claim 18 (depends on 17) The method of claim 17, wherein the upper surface of the second semiconductor device is coplanar with an upper surface of the molding resin at a first plane. ### Claim 19 (depends on 18) The method of claim 18, wherein the one continuous structure is partially exposed at the first plane. ### Claim 20 A method of fabricating a semiconductor package, the method comprising: providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals; stacking the plurality of semiconductor devices on the package substrate at a first temperature, each for a first time, to form a stack structure; simultaneously reflowing the stack structure at a second temperature higher than the first temperature for a second time greater than the first time so that the plurality of semiconductor devices are bonded to the package substrate; and curing the stack structure by cooling, wherein, after the curing, intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate.