# US 12,183,717 B2 · System and method for stacking compression attached memory modules > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,717 B2 - Document ID: US12183717B2 - Status: Granted - Kind: B2 - Application number: 17/863,205 - Filed: 2022-07-12 - Published: 2022-10-27 - Granted: 2024-12-31 - Earliest claimed: 2020-07-22 - Assignees: Dell Products L.P. - Applicants: Dell Products L.P. - Inventors: Arnold Thomas Schnell; Joseph Daniel Mallory - Web page: https://patentgrep.com/patent/US12183717B2 ## CPC - G06F 13/4068: {Electrical coupling} - H10W 90/00: Package configurations - G06F 13/409: {Mechanical coupling (back panels H05K7/1438)} - H05K 1/141: {One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence)} - H10B 12/00: Dynamic random access memory [DRAM] devices - H05K 1/181: associated with surface mounted components - H05K 2201/10159: Memory - H05K 2201/10189: Non-printed connector - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10B: ELECTRONIC MEMORY DEVICES ## Abstract An information handling system includes a first z-axis compression connector having a first depth, a first memory module, a second z-axis compression connector having a second depth that is greater than the first depth, a second memory module, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board at a first location and a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector. A first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector. ## Claims ### Claim 1 An information handling system, comprising: a first z-axis compression connector having a first depth; a first memory module; a second z-axis compression connector having a second depth that is greater than the first depth; a second memory module; and a printed circuit board, wherein a first side of the first compression connector is affixed to the printed circuit board at a first location, a first surface of a first memory circuit board of the first memory module is affixed to a second side of the first compression connector, a first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location, and the first side of a second memory circuit board of the second memory module is affixed to a second side of the second compression connector; wherein the first memory module is accessed via a first memory channel of the information handling system and the second memory module is accessed via a second memory channel of the information handling system. ### Claim 2 (depends on 1) The information handling system of claim 1, wherein: the first compression connector includes an array of first contact elements on the second side of the first compression connector; the first memory module includes an array of first surface contact connections on the first surface of the first memory circuit board, wherein each first surface contact connection is configured to be engaged with an associated one of the first contact elements the second compression connector includes an array of second contact elements on the second side of the second compression connector; and the second memory module includes an array of second surface contact connections on the first surface of the second memory circuit board, wherein each second surface contact connection is configured to be engaged with an associated one of the second contact elements. ### Claim 3 (depends on 2) The information handling system of claim 2, wherein: the first memory module includes a plurality of first memory devices mounted on at least one of the first and second surfaces of the first memory circuit board; the second memory module includes a plurality of second memory devices mounted on at least one of the first surface and a second surface of the second memory circuit board; the first memory devices are arranged to be accessed via the first memory channel; and the second memory devices are arranged to be accessed via the second memory channel. ### Claim 4 (depends on 3) The information handling system of claim 3, wherein the first memory channel includes two memory subchannels. ### Claim 5 (depends on 4) The information handling system of claim 4, wherein a first set of the first surface contact connections associated with a first one of the memory subchannels is arranged as a mirror image of a second set of first surface contact connections associated with a second one of the memory subchannels with respect to a middle row of the surface contact connections. ### Claim 6 (depends on 4) The information handling system of claim 4, wherein a first set of the first surface contact connections associated with a first one of the memory subchannels is arranged as a mirror image of a second set of first surface contact connections associated with a second one of the memory subchannels with respect to a middle column of the surface contact connections. ### Claim 7 (depends on 3) The information handling system of claim 3, wherein the first and second memory modules are each fifth generation Double Data Rate memory modules. ### Claim 8 (depends on 1) The information handling system of claim 1, wherein the first location is offset from the second location by a predetermined distance. ### Claim 9 (depends on 8) The information handling system of claim 8, wherein the first and second memory modules each include a first mounting hole and a second mounting hole that is offset from the first mounting hole by the predetermined distance. ### Claim 10 (depends on 9) The information handling system of claim 9, wherein the first memory module and the second memory module are mounted together to the printed circuit board through the first mounting hole of the first memory module and the second mounting hole of the second memory module. ### Claim 11 A method, comprising: affixing a first side of a first z-axis compression connector to a printed circuit board of an information handling system at a first location, the first compression connector having a first depth; affixing a first surface of a first memory circuit board of a first memory module to a second side of the first compression connector; affixing a first side of a second z-axis compression connector to the printed circuit board at a second location adjacent to the first location, the second compression connector having a second depth that is greater than the first depth; and affixing a first surface of a second memory circuit board of a second memory module to a second side of the second compression connector; wherein the first memory module is accessed via a first memory channel of the information handling system and the second memory module is accessed via a second memory channel of the information handling system. ### Claim 12 (depends on 11) The method of claim 11, further comprising: providing, on the second side of the first compression connector, an array of first contact elements; providing, on the first side of the first memory circuit board, an array of first surface contact connections, wherein each first surface contact connection is configured to be engaged with an associated one of the first contact elements; providing, on the second side of the second compression connector, an array of second contact elements; and providing, on the first surface of the second memory circuit board, an array of second surface contact connections, wherein each second surface contact connection is configured to be engaged with an associated one of the third contact elements. ### Claim 13 (depends on 12) The method of claim 12, further comprising: mounting, on at least one of the first and second surfaces of the first memory circuit board, a plurality of first memory devices; mounting, on at least one of the first and second surfaces of the second memory circuit board, a plurality of second memory devices; accessing, via the first memory channel, the first memory devices; and accessing, via the second memory channel, the second memory devices. ### Claim 14 (depends on 13) The method of claim 13, wherein the first memory channel includes two memory subchannels. ### Claim 15 (depends on 14) The method of claim 14, further comprising: arranging a first set of the first surface contact connections associated with a first one of the memory subchannels as a mirror image of a second set of first surface contact connections associated with a second one of the memory subchannels with respect to a middle row of the surface contact connections. ### Claim 16 (depends on 14) The method of claim 14, further comprising: arranging a first set of the first surface contact connections associated with a first one of the memory subchannels as a mirror image of a second set of first surface contact connections associated with a second one of the memory subchannels with respect to a middle column of the surface contact connections. ### Claim 17 (depends on 13) The method of claim 13, wherein the first and second memory modules are each fifth generation Double Data Rate memory modules. ### Claim 18 (depends on 11) The method of claim 11, wherein: the first location is offset from the second location by a predetermined distance; and the first and second memory modules each include a first mounting hole and a second mounting hole that is offset from the first mounting hole by the predetermined distance. ### Claim 19 (depends on 18) The method of claim 18, wherein the first memory module and the second memory module are mounted together to the printed circuit board through the first mounting hole of the first memory module and the second mounting hole of the second memory module. ### Claim 20 An information handling system, comprising: a processor; a first z-axis compression connector having a first depth; a first memory module including a plurality of first memory devices mounted on at least one of a first surface and second surface of a first memory circuit board of the first memory module; a second z-axis compression connector having a second depth that is greater than the first depth; a second memory module including a plurality of second memory devices mounted on at least one of a first surface and second surface of a second memory circuit board of the second memory module; and a printed circuit board, wherein a first side of the first compression connector is affixed to the printed circuit board at a first location, the first surface of the first memory circuit board is affixed to a second side of the compression connector, a first side of the second compression connector is affixed to the printed circuit board at a second location adjacent to the first location, and the first side of the second memory circuit board is affixed to a second side of the second compression connector; wherein the processor accesses the first memory devices via a first memory channel and accesses the second memory devices via a second memory channel.