# US 12,183,715 B2 · Method for manufacturing semiconductor structure

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- Number: US 12,183,715 B2
- Document ID: US12183715B2
- Status: Granted
- Kind: B2
- Application number: 17/546,283
- Filed: 2021-12-09
- Published: 2022-03-31
- Granted: 2024-12-31
- Earliest claimed: 2020-09-17
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Ting-Cih Kang; Hsih-Yang Chiu
- Web page: https://patentgrep.com/patent/US12183715B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 90/00: Package configurations
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, comprising:
forming a first conductive pad on a first semiconductor device;
forming a second conductive pad on the first conductive pad, wherein an upper surface of the first conductive pad is in direct contact with a bottom surface of the second conductive pad, wherein a width of the second conductive pad is smaller than a width of the first conductive pad;
connecting a second semiconductor device to the first semiconductor device via an adhesive layer; and
forming a via structure in the second semiconductor device, wherein the via structure, having a trapezoid shape, has a width gradually reduced from an upper surface of the via structure to a bottom surface thereof, wherein the upper surface of the via structure is coplanar with an upper surface of the second semiconductor device, wherein the via structure is extended through the adhesive layer at a position that the bottom surface of the via structure contacts an upper surface of the second conductive pad, wherein a width of the bottom surface of the via structure is smaller than the width of the second conductive pad;
wherein the first conductive pad and the second conductive pad are formed of different metal materials;
wherein the forming of the second conductive pad on the first conductive pad comprises: forming a dielectric layer on the first conductive pad; forming an opening in the dielectric layer to expose the first conductive pad; and forming the second conductive pad in the opening, wherein a width of the opening is less than the width of the first conductive pad, wherein the opening is a through opening having a depth equal to a thickness of the dielectric layer, such that the upper surface of the second conductive pad is coplanar with an upper surface of the dielectric layer while a bottom surface of the second conductive pad is coplanar with a bottom surface of the dielectric layer, wherein the upper surface of the second conductive pad is in direct contact with the bottom surface of the via structure while the bottom surface of the second conductive pad is in direct contact with the upper surface of the first conductive pad, wherein the adhesive layer, which is a single layer, has an upper side bonded to a bottom surface of the second semiconductor device and a bottom side bonded to the upper surface of the dielectric layer and the upper surface of the second conductive pad.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the first conductive pad comprises: embedding the first conductive pad in a first semiconductor substrate of the first semiconductor device at a position that the upper surface of the first conductive pad is coplanar with an upper surface of the first semiconductor substrate and a bottom surface of the first conductive pad is located above a bottom surface of the first semiconductor substrate, wherein a height of the first conductive pad is less than a height of the first semiconductor substrate.

### Claim 3 (depends on 1)

The method of claim 1, further comprising: forming the first conductive pad and the second conductive pad with chemical reactivity that increase at positions along a direction from the via structure to the first semiconductor device, wherein the chemical reactivity of the second conductive pad is less than the chemical reactivity of the first conductive pad.

### Claim 4 (depends on 1)

The method of claim 1, further comprising: forming the second conductive pad with a thickness less than a thickness of the first conductive pad, wherein forming the second conductive pad on the first conductive pad comprises: forming a conductive layer on the first conductive pad, and planarizing the conductive layer to coplanar with the upper side of the dielectric layer in order to form the second conductive pad.

### Claim 5 (depends on 1)

The method of claim 1, further comprising: forming a step structure of the first conductive pad and the second conductive pad, wherein a step height of the step structure is less than 1 μm.

### Claim 6 (depends on 1)

The method of claim 1, further comprising: forming the via structure with an aspect ratio less than 10:1.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first conductive pad comprises copper (Cu), aluminum (Al), or a combination thereof.

### Claim 8 (depends on 7)

The method of claim 7, wherein the second conductive pad comprises tungsten (W), gold (Au), silver (Ag), or a combination thereof, wherein forming the second conductive pad on the first conductive pad comprises: filling the second conductive pad on the first conductive pad.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the second conductive pad on the first conductive pad comprises: forming a conductive layer on the first conductive pad, and planarizing the conductive layer to reduce a thickness of the conductive layer in order to form the second conductive pad.

### Claim 10 (depends on 1)

The method of claim 1, wherein the via structure is a through silicon via (TSV).