# US 12,183,713 B2 · Semiconductor module, method for manufacturing same, and semiconductor module mounting body

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- Number: US 12,183,713 B2
- Document ID: US12183713B2
- Status: Granted
- Kind: B2
- Application number: 17/628,004
- Filed: 2019-07-18
- Published: 2022-08-25
- Granted: 2024-12-31
- Earliest claimed: 2019-07-18
- Assignees: Ultramemory Inc.
- Applicants: UltraMemory Inc.
- Inventors: Fumitake Okutsu
- Web page: https://patentgrep.com/patent/US12183713B2

## CPC

- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/037: {Assembling together parts thereof}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor module that enables reduction of manufacturing costs, a method for manufacturing the same, and a semiconductor module mounting body. The semiconductor module having a plurality of stacked dies includes: a first die; a second die disposed side by side with respect to the first die in a direction intersecting with a stacking direction; a third die disposed in the stacking direction, so as to straddle the first die and the second die and that is electrically connected to wiring surfaces of the first die and the second die opposing the third die; projection terminals projecting from the wiring surfaces of the first die and the second die and that project in a space adjacent to at least one of side surfaces of the third die in the direction intersecting with the stacking direction; and rewiring layers disposed so as to overlap with the projection terminals.

## Claims

### Claim 1

A semiconductor module including a plurality of stacked dies, comprising:
a first die;
a second die provided side by side with the first die in a direction intersecting a stacking direction;
a third die that extends over the first die and the second die in the stacking direction, and is electrically connected to wiring surfaces of the first die and the second die opposite to the third die;
at least one projecting terminal which projects from the wiring surfaces of the first die and the second die, and projects in a spatial region adjacent to at least one side surface of the third die in a direction intersecting the stacking direction; and
a rewiring layer which overlaps the projecting terminal,
wherein the third die comprises:
an array portion which overlaps the second die in the stacking direction, and
an interface unit which overlaps the first die in the stacking direction.

### Claim 2 (depends on 1)

The semiconductor module according to claim 1, wherein the second die is a power supply die that supplies the third die with power supplied from the projecting terminal.

### Claim 3

A semiconductor module including a plurality of stacked dies, comprising:
a first die;
a second die provided side by side with the first die in a direction intersecting a stacking direction;
a third die that extends over the first die and the second die in the stacking direction, and is electrically connected to wiring surfaces of the first die and the second die opposite to the third die;
at least one projecting terminal which projects from the wiring surfaces of the first die and the second die, and projects in a spatial region adjacent to at least one side surface of the third die in a direction intersecting the stacking direction; and
a rewiring layer which overlaps the projecting terminal,
wherein the second die comprises a plurality of second dies, and the second dies are provided in a pair with the first die interposed therebetween in a direction intersecting the stacking direction, and the third die comprises a plurality of third dies, and the third dies are provided in a pair, each of which extends over the first die and one of the paired second dies,
the first die has a connection terminal extending from the wiring surface in the stacking direction, and the third die is directly connected to the first die via the connection terminal.

### Claim 4 (depends on 1)

The semiconductor module according to claim 1, further comprising a heat dissipating portion that overlaps the third die, and serves as a heat dissipating path of the third die.

### Claim 5 (depends on 4)

The semiconductor module according to claim 4, further comprising a plurality of external terminals provided side by side with the rewiring layer in the stacking direction, the plurality of external terminals including a connection terminal which is electrically connected to the projecting terminal through the rewiring layer, and a non-connection terminal which is provided at a position overlapping the third die in the stacking direction and is not electrically connected to the projecting terminal.

### Claim 6 (depends on 5)

The semiconductor module according to claim 5, wherein the heat dissipating portion includes an overlapping portion, which overlaps the third die, of the rewiring layer, and the non-connection terminal.

### Claim 7 (depends on 6)

The semiconductor module according to claim 6, wherein the overlapping portion comprises:
metal layers stacked discontinuously, and
at least one heat dissipating via connecting between the metal layers which are adjacent.

### Claim 8 (depends on 4)

The semiconductor module according to claim 4, wherein the heat dissipating portion includes a heat dissipating member penetrating the rewiring layer.

### Claim 9 (depends on 3)

A mounting body of a semiconductor module, comprising:
a semiconductor module according to claim 3, and
a mounting substrate including a plurality of through terminals penetrating in the stacking direction and each connected to at least one external terminal.