# US 12,183,709 B2 · Chip package structure with ring-like structure

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- Number: US 12,183,709 B2
- Document ID: US12183709B2
- Status: Granted
- Kind: B2
- Application number: 18/543,124
- Filed: 2023-12-18
- Published: 2024-04-11
- Granted: 2024-12-31
- Earliest claimed: 2019-06-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Sheng-Yao Yang; Ling-Wei Li; Yu-Jui Wu; Cheng-Lin Huang; Chien-Chen Li; Lieh-Chuan Chen; Che-Jung Chu; Kuo-Chio Liu
- Web page: https://patentgrep.com/patent/US12183709B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/072: {of bump connectors}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 72/01: {Manufacture or treatment}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/354: {comprising polymers}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

## Claims

### Claim 1

A chip structure, comprising:
a chip;
a conductive ring-like structure over and electrically insulated from the chip, wherein the conductive ring-like structure surrounds a central region of the chip; and
a first solder structure over the conductive ring-like structure, wherein the first solder structure and the conductive ring-like structure are made of different materials.

### Claim 2 (depends on 1)

The chip structure as claimed in claim 1, wherein the first solder structure has a ring shape in a top view of the first solder structure.

### Claim 3 (depends on 1)

The chip structure as claimed in claim 1, wherein the first solder structure has a curved top surface.

### Claim 4 (depends on 1)

The chip structure as claimed in claim 1, further comprising:
a conductive bump over and electrically connected to the chip, wherein the conductive bump is in the central region of the chip and electrically insulated from the conductive ring-like structure.

### Claim 5 (depends on 4)

The chip structure as claimed in claim 4, wherein the conductive bump is thicker than the conductive ring-like structure.

### Claim 6 (depends on 4)

The chip structure as claimed in claim 4, wherein the conductive ring-like structure has a line width greater than a width of the conductive bump.

### Claim 7 (depends on 4)

The chip structure as claimed in claim 4, wherein the conductive ring-like structure is between the conductive bump and a sidewall of the chip.

### Claim 8 (depends on 4)

The chip structure as claimed in claim 4, further comprising:
a second solder structure over the conductive bump.

### Claim 9 (depends on 8)

The chip structure as claimed in claim 8, wherein a first top surface of the first solder structure is closer to the chip than a second top surface of the second solder structure.

### Claim 10 (depends on 8)

The chip structure as claimed in claim 8, wherein the first solder structure is wider than the second solder structure.

### Claim 11 (depends on 8)

The chip structure as claimed in claim 8, wherein a first average thickness of the first solder structure is less than a second average thickness of the second solder structure.

### Claim 12

A chip package structure, comprising:
a substrate;
a first conductive bump over the substrate and having a first top surface facing away from the substrate;
a first ring-like structure over the substrate and electrically insulated from the substrate, wherein the first ring-like structure surrounds the first conductive bump, and the first ring-like structure has a second top surface facing away from the substrate; and
a chip bonded to the substrate, wherein the first top surface of the first conductive bump is closer to the chip than the second top surface of the first ring-like structure.

### Claim 13 (depends on 12)

The chip package structure as claimed in claim 12, wherein the first ring-like structure is electrically insulated from the first conductive bump and the chip.

### Claim 14 (depends on 12)

The chip package structure as claimed in claim 12, further comprising:
a second conductive bump connected between the chip and the first conductive bump; and
a second ring-like structure under a bottom surface of the chip and electrically insulated from the chip, wherein the second ring-like structure surrounds the second conductive bump.

### Claim 15 (depends on 14)

The chip package structure as claimed in claim 14, wherein the second ring-like structure is thinner than the second conductive bump.

### Claim 16 (depends on 14)

The chip package structure as claimed in claim 14, wherein the second conductive bump is closer to the substrate than the second ring-like structure.

### Claim 17 (depends on 14)

The chip package structure as claimed in claim 14, further comprising:
an underfill layer between the substrate and the chip, wherein a portion of the underfill layer is between the first ring-like structure and the second ring-like structure.

### Claim 18 (depends on 12)

The chip package structure as claimed in claim 12, further comprising:
an underfill layer between the substrate and the chip, wherein the underfill layer surrounds the first conductive bump and the first ring-like structure, and a portion of the underfill is between the first ring-like structure and the chip.

### Claim 19

A chip package structure, comprising:
a substrate has a first surface and a second surface opposite to the first surface;
a chip over the first surface;
a conductive bump over the second surface and having a first bottom surface facing away from the chip; and
a ring-like structure over the second surface and electrically insulated from the substrate and the chip and having a second bottom surface facing away from the chip, wherein the ring-like structure surrounds the conductive bump, and the second bottom surface of the ring-like structure is closer to the chip than the first bottom surface of the conductive bump.

### Claim 20 (depends on 19)

The chip package structure as claimed in claim 19, further comprising:
a solder ring structure over the second bottom surface of the ring-like structure.