# US 12,183,708 B2 · Double resist structure for electrodeposition bonding

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- Number: US 12,183,708 B2
- Document ID: US12183708B2
- Status: Granted
- Kind: B2
- Application number: 17/588,404
- Filed: 2022-01-31
- Published: 2023-08-03
- Granted: 2024-12-31
- Earliest claimed: 2022-01-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Koki Nakamura; Toyohiro Aoki; Takashi Hisada
- Web page: https://patentgrep.com/patent/US12183708B2

## CPC

- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- C25D 5/022: {using masking means}
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- C25D 17/001: {Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01215: {forming coatings}
- H10W 72/01221: {using local deposition}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/07168: {Means for storing or moving the material for the connector}
- H10W 72/07178: {Means for aligning}
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07231: {Techniques}
- H10W 72/07254: {changes in dispositions}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/257: {Multiple bump connectors having different materials}
- H10W 72/261: {Functions other than electrical connecting}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR

## Abstract

A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.

## Claims

### Claim 1

A semiconductor structure comprising:
a wafer having a wafer outer surface;
a plurality of copper pillars on a semiconductor chip, the plurality of copper pillars having pillar end portions and pillar outside surfaces;
a plurality of copper pads on the wafer, the plurality of copper pads having pad end portions aligned with and directly contacting the pillar end portions, the pillar end portions and the pad end portions of the plurality of copper pads defining a plurality of bonding material receiving regions, the plurality of copper pads having pad outside surfaces, at least one of the pillar end portions and the pad end portions being curved; and
a copper bonding layer on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer, the portions of the outer surface of the wafer surrounding the plurality of copper pads when viewed in plan.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the pillar end portions are curved and the portions of the outer surface of the wafer have an annular shape about the plurality of copper pads when viewed in plan.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the wafer includes a wafer substrate and a wafer seed layer on the wafer substrate, the wafer seed layer forming the wafer outer surface, the plurality of copper pads being located on the wafer seed layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the chip includes a chip substrate and a chip seed layer on the chip substrate, the plurality of copper pillars being located on the chip seed layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the wafer seed layer and the chip seed layer each include an inner titanium layer and an outer copper layer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein at least a portion of the wafer seed layer is recessed under the copper bonding layer but is not recessed under the plurality of copper pads.

### Claim 7 (depends on 2)

The semiconductor structure of claim 2, wherein the plurality of copper pads have a larger diameter than the plurality of copper pillars.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the copper bonding layer includes fillets adjacent to the bonding material receiving regions when viewed in cross section and radially outward thereof when viewed in plan.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the copper bonding layer does not have a scallop shape adjacent to the bonding material receiving regions when viewed in cross section.

### Claim 10 (depends on 2)

The semiconductor structure of claim 2, wherein the plurality of copper pillars have cylindrical protrusions outward of the curved pillar end portions.

### Claim 11 (depends on 2)

The semiconductor structure of claim 2, wherein the plurality of copper pillars have cross-shaped protrusions outward of the curved end portions.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the plurality of copper pillars have elliptical cross sections when viewed in plan.

### Claim 13 (depends on 1)

The semiconductor structure of claim 1, wherein both the pillar end portions and the pad end portions are curved.

### Claim 14 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a plurality of additional semiconductor chips;
an additional plurality of copper pillars on the plurality of additional semiconductor chips, the additional plurality of copper pillars having additional pillar end portions and additional pillar outside surfaces; and
an additional plurality of copper pads on the wafer, the additional plurality of copper pads having additional pad end portions aligned with the additional pillar end portions of the additional plurality of copper pillars on the plurality of additional semiconductor chips, the additional pillar end portions of the additional plurality of copper pillars and the additional pad end portions of the additional plurality of copper pads defining an additional plurality of bonding material receiving regions, the additional plurality of copper pads having additional pad outside surfaces, at least one of the additional pillar end portions of the additional plurality of copper pillars and the additional pad end portions of the additional plurality of copper pads being curved;
wherein the copper bonding layer is also present on the additional pillar outside surfaces of the additional plurality of copper pillars, the additional pad outside surfaces of the additional plurality of copper pads, the additional bonding material receiving regions, and additional portions of the outer surface of the wafer, the additional portions surrounding the additional plurality of copper pads when viewed in plan.

### Claim 15 (depends on 1)

The semiconductor structure of claim 1, wherein the copper bonding layer is disposed directly on the pad outside surfaces.

### Claim 16 (depends on 1)

The semiconductor structure of claim 1, wherein the copper bonding layer is disposed directly on both the pillar outside surfaces and the pad outside surfaces.