# US 12,183,705 B2 · Semiconductor device structure with composite bottle-shaped through silicon via > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,705 B2 - Document ID: US12183705B2 - Status: Granted - Kind: B2 - Application number: 18/217,727 - Filed: 2023-07-03 - Published: 2023-11-02 - Granted: 2024-12-31 - Earliest claimed: 2022-04-27 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Sheng-Hui Yang - Web page: https://patentgrep.com/patent/US12183705B2 ## CPC - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates} - H10W 20/0261: {characterised by the filling method or the material of the conductive fill} - H10W 20/0265: {characterised by the sidewall insulation} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2125: {Top-view shapes} - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01: {Manufacture or treatment} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via. ## Claims ### Claim 1 A semiconductor device structure, comprising: a silicon layer disposed over a first semiconductor die; a first mask layer disposed over the silicon layer; a second semiconductor die disposed over the first mask layer; and a through silicon via penetrating through the silicon layer and the first mask layer; wherein the through silicon via includes a lower conductor, a graphene layer disposed on the lower conductor and an upper conductor disposed in the graphene layer; wherein a bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via; wherein the through silicon via comprises: a conductive layer; and a barrier layer covering sidewalls and a bottom surface of the conductive layer, wherein the barrier layer is in direct contact with the first semiconductor die. ### Claim 2 (depends on 1) The semiconductor device structure of claim 1, wherein the lower conductor of the through silicon via is in direct contact with a first conductive pad in the first semiconductor die, and the upper conductor is in direct contact with a second conductive pad in the second semiconductor die. ### Claim 3 (depends on 2) The semiconductor device structure of claim 2, further comprising: a third conductive pad disposed in the first semiconductor die and adjacent to the first conductive pad; and a fourth conductive pad disposed in the second semiconductor die and adjacent to the second conductive pad, wherein a lateral distance between the third conductive pad and the first conductive pad in the first semiconductor die is greater than a lateral distance between the fourth conductive pad and the second conductive pad in the second semiconductor die. ### Claim 4 (depends on 1) The semiconductor device structure of claim 1, further comprising: a second mask layer disposed between the first mask layer and the second semiconductor die, wherein the through silicon via penetrates through the second mask layer, and wherein the first mask layer and the second mask layer are made of different materials. ### Claim 5 (depends on 4) The semiconductor device structure of claim 4, wherein a sidewall of the second mask layer is inclined relative to a sidewall of the first mask layer. ### Claim 6 (depends on 5) The semiconductor device structure of claim 5, further comprising: a protective layer covering the sidewall of the second mask layer, the sidewall of the first mask layer and an upper sidewall of the silicon layer, wherein the upper sidewall of the silicon layer is substantially aligned with the sidewall of the first mask layer. ### Claim 7 (depends on 6) The semiconductor device structure of claim 6, wherein the through silicon via comprises a lining layer covering sidewalls of the barrier layer. ### Claim 8 A semiconductor device structure, comprising: a silicon layer disposed over a first semiconductor die; a first mask layer disposed over the silicon layer; a second mask layer disposed over the first mask layer; a second semiconductor die disposed over the second mask layer; and a through silicon via penetrating through the silicon layer, the first mask layer and the second mask layer to electrically connect the first semiconductor die and the second semiconductor die; wherein the through silicon via includes a lower conductor, a graphene layer disposed on the lower conductor and an upper conductor disposed in the graphene layer; wherein the through silicon via has a bottle-neck shaped portion surrounded by the first mask layer and an upper portion of the silicon layer, and an interface area between the through silicon via and the first semiconductor die is greater than an interface area between the through silicon via and the second semiconductor die; wherein the through silicon via comprises: a conductive layer; and a barrier layer covering sidewalls and a bottom surface of the conductive layer, wherein the barrier layer is in direct contact with the first semiconductor die. ### Claim 9 (depends on 8) The semiconductor device structure of claim 8, wherein the first semiconductor die has a first critical dimension, and the second semiconductor die has a second critical dimension, and the first critical dimension is greater than the second critical dimension. ### Claim 10 (depends on 8) The semiconductor device structure of claim 8, wherein the through silicon via further comprises: a top portion surrounded by the second mask layer; and a bottom portion surrounded by a lower portion of the silicon layer, wherein the bottle-neck shaped portion of the through silicon via is sandwiched between the top portion and the bottom portion of the through silicon via, and the top portion of the through silicon via has a tapered profile tapering toward the bottle-neck shaped portion of the through silicon via. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the bottom portion of the through silicon via has rounded and convex top corners. ### Claim 12 (depends on 10) The semiconductor device structure of claim 10, wherein the bottle-neck shaped portion and the top portion of the through silicon via are separated from the first mask layer, the second mask layer and the upper portion of the silicon layer by a protective layer. ### Claim 13 (depends on 12) The semiconductor device structure of claim 12, wherein the bottom portion of the through silicon via is in direct contact with the lower portion of the silicon layer. ### Claim 14 (depends on 12) The semiconductor device structure of claim 12, wherein the protective layer comprises aluminum oxide.