# US 12,183,704 B2 · Semiconductor package and method for manufacturing the same

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- Number: US 12,183,704 B2
- Document ID: US12183704B2
- Status: Granted
- Kind: B2
- Application number: 17/524,720
- Filed: 2021-11-11
- Published: 2022-05-12
- Granted: 2024-12-31
- Earliest claimed: 2020-11-11
- Assignees: Nepes Co., Ltd.; Nepes Laweh Corporation
- Applicants: Nepes Co., Ltd.; Nepes Laweh Corporation
- Inventors: Byung Cheol Kim; Yong Tae Kwon; Hyo Gi Jo; Dong Hoon Oh; Jae Cheon Lee; Hyung Jin Shin; Mary Maye Melgo Galimba
- Web page: https://patentgrep.com/patent/US12183704B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/103: {alphanumeric information, e.g. words, letters or serial numbers}
- H10W 46/106: {digital information, e.g. bar codes}
- H10W 46/401: {for identification or tracking}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure. Also, a top surface of the molding layer, a top surface of the conductive post, and a top surface of the first adhesive layer may be coplanar.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor chip having a bottom surface adjacent to a first active layer and a top surface opposite to the bottom surface;
a first adhesive layer disposed on the top surface of the first semiconductor chip;
a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer;
a first conductive post disposed outside the first semiconductor chip;
a redistribution structure disposed under the first semiconductor chip and comprising a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern;
a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure,
a second semiconductor chip disposed under the first semiconductor chip, having a cross-sectional area in a horizontal direction smaller than a cross-sectional area of the first semiconductor chip in the horizontal direction, and having a bottom surface adjacent to a second active layer and a top surface opposite to the bottom surface;
a second adhesive layer disposed between the first semiconductor chip and the second semiconductor chip;
a second conductive stud disposed on the bottom surface of the second semiconductor chip to be inside the first conductive stud as seen in a cross-sectional view and electrically connected to the second active layer;
a support pad disposed on a top surface of the first adhesive layer; and
a connection pad disposed on the first conductive post,
wherein the redistribution pattern of the redistribution structure is connected to the second conductive stud,
wherein the first conductive stud includes a portion that overlaps the second conductive stud and the first conductive post along the horizontal direction, and
wherein a top surface of the molding layer, a top surface of the support pad, and a top surface of the connection pad are coplanar, and a bottom surface of the support pad is coplanar with the top surface of the first adhesive layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first conductive stud includes a portion that overlaps the second semiconductor chip along the horizontal direction.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the top surface of the first adhesive layer comprises a marking region comprising at least any one of information comprising a type, a number, performance, a manufacturing company, a logo, a manufactured date, and a serial number of the first semiconductor chip.

### Claim 4 (depends on 1)

The semiconductor package of claim 1,
wherein a length of the first conductive stud in a vertical direction is greater than a length of the second conductive stud in the vertical direction,
a length of the first conductive stud in the vertical direction is smaller than a length of the first conductive post in the vertical direction, and
wherein the first conductive post includes a first portion overlapping the first semiconductor chip and a second portion overlapping the second semiconductor chip along the horizontal direction.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising:
a third semiconductor chip disposed on a side of the first semiconductor chip and having a bottom surface adjacent to a third active layer and a top surface opposite to the bottom surface;
a third adhesive layer disposed on the top surface of the third semiconductor chip; and
a third conductive stud disposed on the bottom surface of the third semiconductor chip and electrically connected to the third active layer,
wherein the top surface of the molding layer is coplanar with a top surface of the third adhesive layer.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein a first vertex formed as a bottom surface and a side surface of the redistribution structure meet is disposed inside a second vertex formed as a top surface and the side surface of the redistribution structure meet.