# US 12,183,702 B2 · Electronic package with varying interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,702 B2 - Document ID: US12183702B2 - Status: Granted - Kind: B2 - Application number: 17/645,424 - Filed: 2021-12-21 - Published: 2023-06-22 - Granted: 2024-12-31 - Earliest claimed: 2021-12-21 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kamal K. Sikka; Charles Leon Arvin; Thomas Edward Lombardi; Piyas Bal Chowdhury; Alfred Grill; Steven Lorenz Wright - Web page: https://patentgrep.com/patent/US12183702B2 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/232: {Plan-view shape, i.e. in top view} - H10W 72/237: {Multiple bump connectors having different shapes} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas. ## Claims ### Claim 1 An electronic package comprising: a device layer; a substrate layer; and an interconnect layer positioned between the device layer and the substrate layer, the interconnect layer comprising a plurality of solder bumps arranged with a uniform pitch, wherein: a first subset of the plurality of solder bumps comprises solder bumps each having a first cross-sectional area, the first subset arranged along a first position at a first edge of the interconnect layer, a second subset of the plurality of solder bumps comprises one or more solder bumps each having a second cross-sectional area, the second subset arranged at a second position of the interconnect layer, and a third subset of the plurality of solder bumps is arranged between the first position and the second position, the third subset comprising solder bumps having one or more third cross-sectional areas that cause underfill material, when dispensed into the interconnect layer at the first edge, to flow by capillary action in a flow direction from the first subset toward the second subset, wherein at least one of the one or more third cross-sectional areas is less than the first cross-sectional area and greater than the second cross-sectional area, and wherein the cross-sectional areas of the plurality of solder bumps monotonically decrease along the flow direction. ### Claim 2 (depends on 1) The electronic package of claim 1, further comprising: the underfill material in the interconnect layer, wherein the underfill material is positioned between the plurality of solder bumps such that the underfill material fills a space between the device layer and the substrate layer. ### Claim 3 (depends on 1) The electronic package of claim 1, wherein the first subset, the second subset, and the third subset comprise a similar cross-sectional shape, wherein the similar cross-sectional shape comprises a circular shape. ### Claim 4 (depends on 1) The electronic package of claim 1, wherein the first subset, the second subset, and the third subset comprise a similar cross-sectional shape, wherein the similar cross-sectional shape comprises an elliptical shape. ### Claim 5 (depends on 1) The electronic package of claim 1, wherein the first subset comprises a circular cross-sectional shape, the second subset comprises an elliptical cross-sectional shape, and the third subset comprises varying elliptical cross-sectional shapes. ### Claim 6 (depends on 1) The electronic package of claim 1, wherein the plurality of solder bumps further comprise a fourth subset, wherein the fourth subset comprises a plurality of fine cross-sectional areas, wherein the fine cross-sectional areas comprise smaller areas than the plurality of solder bumps in surrounding subsets, and wherein within the plurality of fine cross-sectional areas, individual fine cross-sectional areas decrease along the flow direction from the first position to the second position. ### Claim 7 (depends on 1) The electronic package of claim 1, wherein the electronic package comprises a dual chip module comprising a second plurality of solder bumps arranged in the interconnect layer, wherein: a first subset of the second plurality of solder bumps comprises the first cross-sectional area, and wherein the first subset of the second plurality of solder bumps is arranged along a third position at a second edge of the interconnect layer, a second subset of the second plurality of solder bumps comprises the second cross-sectional area, and wherein the second subset of the second plurality of solder bumps is arranged at a fourth position of the interconnect layer, and a third subset of the second plurality of solder bumps is arranged between the third position and the fourth position, wherein the third subset of the second plurality of solder bumps comprises a plurality of cross-sectional areas, wherein within the plurality of cross-sectional areas, individual cross-sectional areas decrease along a second flow direction from the third position to the fourth position. ### Claim 8 (depends on 1) The electronic package of claim 1, wherein the electronic package comprises a quad chip module comprising more than two pluralities of solder bumps arranged in the interconnect layer, wherein each of the two pluralities of solder bumps comprise subsets arranged with a plurality of cross-section areas, and wherein within the plurality of cross-section areas, individual cross-sectional areas decrease along one or more underfill flow directions in the interconnect layer. ### Claim 9 (depends on 1) The electronic package of claim 1, wherein the device layer comprises a first plurality of C4 pillars, wherein the substrate layer comprises a second plurality of C4 pillars, and wherein the plurality of solder bumps provides a connection between the first and second plurality of C4 pillars. ### Claim 10 An interconnect layer for an electronic device comprising: a plurality of solder bumps arranged with a uniform pitch, wherein: a first subset of the plurality of solder bumps comprises solder bumps each having a first cross-sectional area, and wherein the first subset is arranged along a first position at a first edge of the interconnect layer, a second subset of the plurality of solder bumps comprises one or more solder bumps each having a second cross-sectional area, and wherein the second subset is arranged at a second position of the interconnect layer, and the plurality of solder bumps have a plurality of cross-sectional areas, wherein individual cross-sectional areas decrease along an underfill flow direction from the first position to the second position, the plurality of cross-sectional areas causing underfill material, when dispensed into the interconnect layer at the first edge, to flow by capillary action in the underfill flow direction, wherein at least one of the plurality of solder bumps arranged between the first subset and the second subset has a third cross-sectional area that is less than the first cross-sectional area and greater than the second cross-sectional area, and wherein the cross-sectional areas of the plurality of solder bumps monotonically decrease along the underfill flow direction. ### Claim 11 (depends on 10) The interconnect layer of claim 10, further comprising: the underfill material in the interconnect layer, wherein the underfill material is positioned between the plurality of solder bumps such that the underfill material fills a space between the a device layer and a substrate layer in an electronic package. ### Claim 12 (depends on 10) The interconnect layer of claim 10, wherein the first subset and the second subset comprise a similar cross-sectional shape, wherein the similar cross-sectional shape comprises a circular shape. ### Claim 13 (depends on 10) The interconnect layer of claim 10, wherein the first subset, the second subset, and the third subset comprise a similar cross-sectional shape, wherein the similar cross-sectional shape comprises an elliptical shape. ### Claim 14 (depends on 10) The interconnect layer of claim 10, wherein the first subset comprises a circular cross-sectional shape, the second subset comprises an elliptical cross-sectional shape, and the third subset comprises varying elliptical cross-sectional shapes. ### Claim 15 (depends on 10) The interconnect layer of claim 10, wherein the plurality of solder bumps further comprise a fourth subset, wherein the fourth subset comprises a plurality of fine cross-sectional areas, wherein the fine cross-sectional areas comprise smaller areas than the plurality of solder bumps in surrounding subsets, and wherein within the plurality of fine cross-sectional areas, individual fine cross-sectional areas decrease along the underfill flow direction from the first position to the second position. ### Claim 16 (depends on 10) The interconnect layer of claim 10, wherein the interconnect layer comprises an interconnect layer in a dual chip module comprising a second plurality solder bumps arranged in the interconnect layer, wherein: a first subset of the second plurality of solder bumps comprises the first cross-sectional area, and wherein the first subset of the second plurality of solder bumps is arranged along a third position at a second edge of the interconnect layer, a second subset of the second plurality of solder bumps comprises the second cross-sectional area, and wherein the second subset of the second plurality of solder bumps is arranged at a fourth position of the interconnect layer, and a third subset of the second plurality of solder bumps is arranged between the third position and the fourth position, wherein the third subset of the second plurality of solder bumps comprises a plurality of cross-sectional areas, wherein within the plurality of cross-sectional areas, individual cross-sectional areas decrease along a second underfill flow direction from the third position to the fourth position. ### Claim 17 (depends on 10) The interconnect layer of claim 10, wherein the interconnect layer comprises an interconnect layer in comprises a quad chip module comprising a more than two pluralities of solder bumps arranged in the interconnect layer, wherein each of the two pluralities of solder bumps comprise subsets arranged with a plurality of cross-section areas, and wherein within the plurality of cross-section areas, individual cross-sectional areas decreases along one or more underfill flow directions in the interconnect layer. ### Claim 18 A method comprising: during a first plating process, forming a first plurality of C4 pillars on a first structure, wherein the first plurality of C4 pillars comprise a plurality of cross-sectional areas, wherein within the plurality of cross-sectional areas, individual cross-sectional areas monotonically decrease along an underfill flow direction between a first subset of the first plurality of C4 pillars to a second subset of the first plurality of C4 pillars, the plurality of cross-sectional areas comprising a first cross-sectional area of the first subset, a second cross-sectional area of the second subset, and at least one intermediate cross-sectional area; during a second plating process, forming a plurality of solder plates on the C4 pillars, wherein each solder plate of the plurality of solder plates comprises a mass of solder corresponding to a cross-sectional area of a respective C4 pillar on which the solder plate is formed, wherein the mass of solder provides for a consistent interconnect height upon solder reflow; and during a finishing process, forming a plurality of solder bump interconnects between the first plurality of C4 pillars on the first structure and a plurality of contacts on a second structure, the plurality of solder bump interconnects having a uniform pitch, the plurality of cross-sectional areas causing underfill material, when dispensed between the first structure and the second structure, to flow by capillary action in the underfill flow direction. ### Claim 19 (depends on 18) The method of claim 18, further comprising: providing the underfill material to the plurality of solder bump interconnects, wherein the underfill material flows along the underfill flow direction and fills a space between the first structure and the second structure and between the plurality of solder bump interconnects. ### Claim 20 (depends on 19) The method of claim 19, wherein the first plating process comprises a photo-resist process, and wherein the second plating process comprises a liquid resist process.