# US 12,183,701 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,701 B2 - Document ID: US12183701B2 - Status: Granted - Kind: B2 - Application number: 18/471,358 - Filed: 2023-09-21 - Published: 2024-01-11 - Granted: 2024-12-31 - Earliest claimed: 2016-09-28 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Bungo Tanaka; Keiji Wada; Satoshi Kageyama - Web page: https://patentgrep.com/patent/US12183701B2 ## CPC - H10W 70/457: {of metallic layers on leadframes} - H10W 20/42: Vias, e.g. via plugs - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 72/019: {of bond pads} - H10W 72/90: Bond pads, in general - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/07336: {Soldering or alloying} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer. ## Claims ### Claim 1 A semiconductor device comprising: an insulating layer; a first metal layer arranged over the insulating layer; a second metal layer that is arranged over a part of the first metal layer and that includes a Cu layer, an Ni layer and a surface metal layer laminated in that order from the first metal layer; and a resin that selectively coats the second metal layer; wherein the Ni layer has a thickness smaller than a thickness of the Cu layer, and the surface metal layer has a thickness smaller than a thickness of the Ni layer and is exposed from the resin. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the resin has an opening selectively exposing the surface metal layer. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the resin has a portion that covers the first metal layer and the Cu layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the resin has a portion that covers a side wall portion of the first metal layer. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the resin has a portion that is arranged in a region between the first metal layer and the Cu layer. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the second metal layer has a recess portion that is formed in the Cu layer and is hollowed inward of the Cu layer, and the resin is arranged in the recess portion. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the recess portion is formed on a lower end side of the Cu layer and exposes the first metal layer, and the recess portion fills the recess portion between the first metal layer and the Cu layer. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second metal layer has a curved portion on a lower end side of the Cu layer, and the resin has a portion covering the curved portion. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the Cu layer includes a side surface that has a portion extending in a linear shape on an upper end side as viewed in cross section. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the Cu layer has a portion that is positioned outward from a periphery of the first metal layer. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the Cu layer has a width greater than a width of the first metal layer. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the Ni layer has a portion that is positioned outward from a periphery of the first metal layer. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the Ni layer has a width greater than a width of the first metal layer as viewed in cross section. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the surface metal layer has a portion that is positioned outward from a periphery of the first metal layer. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the surface metal layer has a width greater than a width of the first metal layer as viewed in cross section. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the first metal layer has a thickness smaller than a thickness of the insulating layer. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the insulating layer includes at least one of an oxide film and a nitride film. ### Claim 18 (depends on 1) The semiconductor device according to claim 1, wherein the surface metal layer includes a palladium layer. ### Claim 19 (depends on 1) The semiconductor device according to claim 1, wherein the surface metal layer has a surface to which a wire is to be connected. ### Claim 20 (depends on 1) The semiconductor device according to claim 1, further comprising: a wire electrically connected to the second metal layer.