# US 12,183,699 B2 · 3D semiconductor device and structure with logic circuits and memory cells

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- Number: US 12,183,699 B2
- Document ID: US12183699B2
- Status: Granted
- Kind: B2
- Application number: 18/106,484
- Filed: 2023-02-07
- Published: 2023-06-15
- Granted: 2024-12-31
- Earliest claimed: 2018-09-04
- Assignees: Monolithic 3D Inc.
- Applicants: Monolithic 3D Inc.
- Inventors: Zvi Or-Bach; Jin-Woo Han; Brian Cronquist
- Web page: https://patentgrep.com/patent/US12183699B2

## CPC

- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10B 12/50: {Peripheral circuit region structures}
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 72/0198: {batch processes}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07554: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/853: {On the same surface}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/163: {using active alignment, e.g. detecting marks and correcting position}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/732: {having shape changed during the connecting}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

## Claims

### Claim 1

A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds; and
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

### Claim 2 (depends on 1)

The 3D device according to claim 1,
wherein said single crystal silicon comprises channels adapted for fluid cooling.

### Claim 3 (depends on 1)

The 3D device according to claim 1, further comprising:
a third level,
wherein said third level comprises a plurality of RF circuits.

### Claim 4 (depends on 1)

The 3D device according to claim 1,
wherein said single crystal silicon comprises an area, and
wherein said area is greater than 1,000 mm2.

### Claim 5 (depends on 1)

The 3D device according to claim 1,
wherein said device comprises a plurality of transmission lines.

### Claim 6 (depends on 1)

The 3D device according to claim 1,
wherein said memory cells comprise Dynamic Random Access Memory (“DRAM”) cells.

### Claim 7 (depends on 1)

The 3D device according to claim 1,
wherein said memory cells comprise non-volatile memory cells.

### Claim 8

A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds,
wherein said single crystal silicon comprises an area, and
wherein said area is greater than 1,000 mm2; and
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

### Claim 9

A 3D semiconductor device, the device comprising:
a first level; and
a second level,
wherein said first level comprises single crystal silicon and a plurality of logic circuits,
wherein said plurality of logic circuits each comprise first transistors,
wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells,
wherein said second level comprises a plurality of second transistors,
wherein each of said memory cells comprises at least one of said second transistors,
wherein said first level is bonded to said second level,
wherein said bonded comprises regions of oxide to oxide bonds,
wherein said bonded comprises regions of metal to metal bonds,
wherein said single crystal silicon comprises an area, and
wherein said memory cells comprise Dynamic Random Access Memory (“DRAM”) cells;
a thermal isolation layer disposed between said first level and said second level,
wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.