# US 12,183,697 B2 · Semiconductor device having a metal pad and a protective layer for corrosion prevention due to exposure to halogen

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- Number: US 12,183,697 B2
- Document ID: US12183697B2
- Status: Granted
- Kind: B2
- Application number: 18/329,128
- Filed: 2023-06-05
- Published: 2023-10-05
- Granted: 2024-12-31
- Earliest claimed: 2019-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Fan Huang; Yen-Ming Chen; Chih-Sheng Li; Hui-Chi Chen; Chih-Hung Lu; Dian-Hau Chen
- Web page: https://patentgrep.com/patent/US12183697B2

## CPC

- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 74/147: {the encapsulations being multilayered}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6514: {by exposure to a plasma}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10D 1/692: {Electrodes}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

## Claims

### Claim 1

A semiconductor device, comprising:
a metal pad over a substrate;
a first dielectric layer disposed directly on the metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer and the metal pad;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the metal pad, the polymeric material and the protective layer,
wherein a portion of the protective layer is in direct contact with a top surface of the metal pad.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal pad comprises aluminum or an aluminum alloy.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises undoped silicate glass.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer comprises silicon nitride.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the protective layer is in contact with sidewalls of the first dielectric layer and the second dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the polymeric material comprises halogen.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the polymeric material comprises fluorine or chlorine.

### Claim 8

A semiconductor structure, comprising:
a passivation structure;
a passive device disposed in the passivation structure;
a contact via extending through the passivation structure and the passive device;
a metal pad disposed over the passivation structure and electrically coupled to the contact via;
a first dielectric layer disposed directly on the metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the metal pad, the polymeric material and the protective layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the protective layer is in contact with a top surface of the metal pad.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the polymeric material is spaced apart from the first dielectric layer and the second dielectric layer by the protective layer.

### Claim 11 (depends on 8)

The semiconductor structure of claim 8, wherein the passive device comprises an metal-insulator-metal (MIM) structure.

### Claim 12 (depends on 8)

The semiconductor structure of claim 8, wherein the metal pad comprises aluminum.

### Claim 13 (depends on 8)

The semiconductor structure of claim 8, wherein the first dielectric layer is in contact with a top surface of the passivation structure and sidewalls of the metal pad.

### Claim 14 (depends on 8)

The semiconductor structure of claim 8, wherein the polymeric material comprises CF3 functional groups.

### Claim 15 (depends on 8)

The semiconductor structure of claim 8, wherein the bump feature comprises:
a metallization layer;
a bump layer over the metallization layer; and
a solder layer over the bump layer.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15,
wherein the metallization layer and the bump layer comprise copper,
wherein a copper content of the bump layer is greater than a copper content of the metallization layer.

### Claim 17

A semiconductor structure, comprising:
an aluminum-containing metal pad over a substrate;
a first dielectric layer disposed directly on the aluminum-containing metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer and the aluminum-containing metal pad;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the aluminum-containing metal pad, the polymeric material and the protective layer,
wherein the polymeric material is spaced apart from a top surface of the aluminum-containing metal pad by the protective layer,
wherein sidewalls of the first dielectric layer and the second dielectric layer are spaced apart from the bump feature by the protective layer and the polymeric material.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein the protective layer comprises a thickness between about 50 Å and about 200 Å.

### Claim 19 (depends on 17)

The semiconductor structure of claim 17, wherein the polymeric material comprises fluorine or chlorine.

### Claim 20 (depends on 17)

The semiconductor structure of claim 17, wherein the protective layer comprises silicon oxide or silicon nitride.