# US 12,183,696 B2 · Semiconductor device including bonding pad metal layer structure

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- Number: US 12,183,696 B2
- Document ID: US12183696B2
- Status: Granted
- Kind: B2
- Application number: 18/235,585
- Filed: 2023-08-18
- Published: 2023-12-07
- Granted: 2024-12-31
- Earliest claimed: 2020-08-18
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Evelyn Napetschnig; Jens Brandenburg; Christoffer Erbert; Joachim Hirschler; Oliver Humbel; Thomas Rupp; Carsten Schaeffer; Julia Zischang
- Web page: https://patentgrep.com/patent/US12183696B2

## CPC

- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/4407: {Aluminium alloys}
- H10W 20/4424: {Copper alloys}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a wiring metal layer structure;
forming a dielectric layer structure arranged directly on the wiring metal layer structure; and
forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure,
wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure,
wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a passivation layer structure on at least part of the wiring metal layer structure before forming the dielectric layer structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the dielectric layer structure and forming the bonding pad metal layer structure include:
forming a dielectric layer on the wiring metal layer structure and on the passivation layer structure;
patterning the dielectric layer in a central part of a bonding pad area; and
after patterning the dielectric layer in the central part, forming a bonding pad metal layer on the dielectric layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming the bonding pad metal layer structure by patterning the bonding pad metal layer,
wherein patterning the bonding pad metal layer includes an etch process using the dielectric layer as an etch stop layer.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
patterning the dielectric layer in a part surrounding the central part of the bonding pad area after forming the bonding pad metal layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the bonding pad metal layer structure or a portion of the bonding pad metal layer comprises Al by at least 50% of the amount of substance.

### Claim 7 (depends on 6)

The method of claim 6, wherein the wiring metal layer structure or a portion of the wiring metal layer structure comprises Al by at least 50% of the amount of substance.

### Claim 8 (depends on 1)

The method of claim 1, wherein the wiring metal layer structure or the portion of the wiring metal layer structure includes a first metal compound of at least Cu and Al, or AlSiCu.

### Claim 9 (depends on 1)

The method of claim 1, wherein the bonding pad metal layer structure or the portion of the bonding pad metal layer includes a second metal compound of at least Cu and Al.

### Claim 10 (depends on 1)

The method of claim 1, wherein the wiring metal layer structure or the portion of the wiring metal layer structure includes AlSiCu, and wherein the bonding pad metal layer structure or the portion of the bonding pad metal layer structure includes AlCu.

### Claim 11 (depends on 1)

The method of claim 1, wherein the layer thickness of the dielectric layer structure ranges from 50 nm to 1 μm.

### Claim 12 (depends on 1)

The method of claim 1, wherein a lateral end of the dielectric layer structure laterally protrudes from a lateral end of the bonding pad metal layer structure.

### Claim 13 (depends on 1)

The method of claim 1, wherein the wiring metal layer structure is formed to directly adjoin a surface of a semiconductor body.

### Claim 14 (depends on 1)

The method of claim 1, wherein the dielectric layer structure comprises any one of or any combination of an oxide layer, a silicon oxynitride layer, a nitride layer, and an undoped polycrystalline silicon layer.

### Claim 15 (depends on 1)

The method of claim 1, wherein the semiconductor device is a power semiconductor device.

### Claim 16 (depends on 1)

The method of claim 1, wherein the bonding pad metal layer structure includes a central part and a peripheral part, and wherein the method comprises forming a wire bond on the bonding pad metal layer structure that is located in the central part.

### Claim 17 (depends on 16)

The method of claim 16, wherein a number of wire bonds on the bonding pad metal layer structure is equal to two or larger.

### Claim 18 (depends on 16)

The method of claim 16, wherein the dielectric layer structure includes a closed peripheral part.

### Claim 19 (depends on 18)

The method of claim 18, wherein the dielectric layer structure includes a central part that is laterally spaced from the closed peripheral part by a separative opening in the dielectric layer structure.

### Claim 20 (depends on 19)

The method of claim 19, wherein a maximum lateral extent of the openings in the central part of the dielectric layer structure is smaller than a sum of the layer thickness of the wiring metal layer structure and the layer thickness of the bonding pad metal layer structure.

### Claim 21 (depends on 19)

The method of claim 19, wherein a minimum lateral extent of the openings in the central part of the dielectric layer structure is equal to or larger than two times the layer thickness of the dielectric layer structure.

### Claim 22 (depends on 19)

The method of claim 19, wherein the dielectric layer structure covers 25% to 90% of a bottom of the bonding pad metal layer structure in the central part of the bonding pad metal layer structure.

### Claim 23 (depends on 1)

The method of claim 1, wherein the bonding pad metal layer structure or a portion of the bonding pad metal layer structure comprises copper.

### Claim 24 (depends on 1)

The method of claim 1, wherein the wiring metal layer structure or a portion of the wiring metal layer structure comprises copper.

### Claim 25 (depends on 1)

The method of claim 1, wherein both the bonding pad metal layer structure and the wiring metal layer structure comprise copper.