# US 12,183,695 B2 · Method of manufacturing package structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,695 B2 - Document ID: US12183695B2 - Status: Granted - Kind: B2 - Application number: 17/815,244 - Filed: 2022-07-27 - Published: 2022-11-17 - Granted: 2024-12-31 - Earliest claimed: 2020-10-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Jen-Yuan Chang; Chia-Ping Lai - Web page: https://patentgrep.com/patent/US12183695B2 ## CPC - H10W 72/019: {of bond pads} - H10W 90/00: Package configurations - H10W 72/013: {of die-attach connectors} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 72/01931: {using blanket deposition} - H10W 72/01953: {by etching} - H10W 72/07236: {Soldering or alloying} - H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting} - H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core} - H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/941: {Dispositions of bond pads} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids} - H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads} - H10W 72/967: {Multiple bond pads having different functions} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/334: {Thermocompression bonding} - H10W 90/20: Configurations of stacked chips - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a package structure is provided. The method of manufacturing a package structure comprises receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer on each semiconductor structure; forming at least one supporting structure and at least one pad trench in the isolation layer; filling the pad trench with electrically conductive material; planarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures. ## Claims ### Claim 1 A method of manufacturing a package structure, comprising receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer on each semiconductor structure; forming at least one supporting structure and at least one pad trench in the isolation layer; filling the pad trench with electrically conductive material; planarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures, wherein each bonding pad has a bonding surface including a bonding region and at least one buffer region; and a ratio of a surface area of the buffer region to that of the bonding region is from about 0.01 to about 10. ### Claim 2 (depends on 1) The method of claim 1, wherein materials of the supporting structures are identical to those of the isolation layer. ### Claim 3 (depends on 1) The method of claim 1, wherein materials of the supporting structures have lower polishing rate selectivity than those of the electrically conductive structure. ### Claim 4 (depends on 1) The method of claim 1, further comprising forming an electrically conductive interlayer along a bottom and sidewalls of the pad trench and supporting structures after forming of the at least one supporting structure and at least one pad trench. ### Claim 5 (depends on 1) The method of claim 1, wherein bonding the semiconductor structures comprises contacting the bonding surface of the bonding layer on the first semiconductor structure with the bonding surface of the bonding layer on the second semiconductor structure; wherein the bonding pad of the first semiconductor structure has a first central axis and the bonding pad of the second semiconductor structure has a second central axis; and wherein an angle between the first central axis and the second central axis is larger than 0° and less than 180°. ### Claim 6 (depends on 1) The method of claim 1, wherein bonding the semiconductor structures comprises bonding the bonding layer of the first semiconductor structure and the bonding layer of the second semiconductor structure by hybrid bonding with application of heat and/or pressure. ### Claim 7 (depends on 1) The method of claim 1, wherein the supporting structure is made of dielectric materials, and the supporting structure is from about 0.1% in volume to about 80% in volume based on the total volume of the bonding pad. ### Claim 8 A method of manufacturing a package structure, comprising receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer with a recess on each semiconductor structure, so that the semiconductor structure exposed from the recess; forming a supporting material layer in the at least one recess to cover the exposed portion of the semiconductor structure; removing a portion of the supporting material layer to form at least one supporting structure and at least one pad trench in the isolation layer; filling the pad trench with an electrically conductive material; planarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures, wherein each bonding pad has a bonding surface including a bonding region and at least one buffer region; and a ratio of a surface area of the buffer region to that of the bonding region is from about 0.01 to about 10. ### Claim 9 (depends on 8) The method of claim 8, wherein materials of the supporting structure are identical to those of the isolation layer. ### Claim 10 (depends on 8) The method of claim 8, wherein materials of the supporting structures have lower polishing rate selectivity than those of the electrically conductive structure. ### Claim 11 (depends on 8) The method of claim 8, wherein bonding the semiconductor structures comprises contacting the bonding surface of the bonding layer on the first semiconductor structure with the bonding surface of the bonding layer on the second semiconductor structure; wherein the bonding pad of the first semiconductor structure has a first central axis and the bonding pad of the second semiconductor structure has a second central axis; and wherein an angle between the first central axis and the second central axis is larger than 0° and less than 180°. ### Claim 12 (depends on 8) The method of claim 8, wherein bonding the semiconductor structures comprises bonding the bonding layer of the first semiconductor structure and the bonding layer of the second semiconductor structure by hybrid bonding with application of heat and/or pressure. ### Claim 13 (depends on 8) The method of claim 8, wherein the supporting structure is made of dielectric materials, and the supporting structure is from about 0.1% in volume to about 80% in volume based on the total volume of the bonding pad. ### Claim 14 A method of manufacturing a package structure, comprising receiving a first semiconductor structure and a second semiconductor structure; forming an isolation layer with a recess on each semiconductor structure, so that the semiconductor structure exposed from the recess; forming a supporting material layer in the at least one recess to cover the exposed portion of the semiconductor structure; removing a portion of the supporting material layer to form at least one supporting structure and at least one pad trench in the isolation layer; forming an electrically conductive interlayer along a bottom and a sidewall of the pad trench and a top of the supporting structure; filling the pad trench with electrically conductive material; planarizing the isolation layer and the electrically conductive material to form bonding pads in a bonding layer on each semiconductor structure; and bonding the semiconductor structures, wherein each bonding pad has a bonding surface including a bonding region and at least one buffer region; and a ratio of a surface area of the buffer region to that of the bonding region is from about 0.01 to about 10. ### Claim 15 (depends on 14) The method of claim 14, wherein materials of the supporting structure are identical to those of the isolation layer. ### Claim 16 (depends on 14) The method of claim 14, wherein materials for the supporting structure, materials for the electrically conductive structure and materials for the electrically conductive interlayer are different. ### Claim 17 (depends on 14) The method of claim 14, wherein materials of the supporting structures have lower polishing rate selectivity than those of the electrically conductive structure. ### Claim 18 (depends on 14) The method of claim 14, wherein bonding the semiconductor structures comprises contacting the bonding surface of the bonding layer on the first semiconductor structure with the bonding surface of the bonding layer on the second semiconductor structure; wherein the bonding pad of the first semiconductor structure has a first central axis and the bonding pad of the second semiconductor structure has a second central axis; and wherein an angle between the first central axis and the second central axis is larger than 0° and less than 180°. ### Claim 19 (depends on 18) The method of claim 18, wherein the angle between the first central axis and the second central axis is about 90°. ### Claim 20 (depends on 14) The method of claim 14, wherein the supporting structure is made of dielectric materials, and the supporting structure is from about 0.1% in volume to about 80% in volume based on the total volume of the bonding pad.