# US 12,183,692 B1 · Embedded inductors and integrated voltage regulators for packaged semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,692 B1 - Document ID: US12183692B1 - Status: Granted - Kind: B1 - Application number: 18/404,535 - Filed: 2024-01-04 - Granted: 2024-12-31 - Earliest claimed: 2024-01-04 - Assignees: Saras Micro Devices, Inc. - Applicants: Saras Micro Devices, Inc. - Inventors: Carlos Riera; Bartlet H. DeProspo; Urmi Ray - Web page: https://patentgrep.com/patent/US12183692B1 ## CPC - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package substrate for a semiconductor device includes a first substrate core and an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core and one or more second segments defined by one or more conductive vias extending through the first substrate core. The package substrate may further include a capacitor embedded in the first substrate core and/or in a second substrate core vertically stacked with the first substrate core. ## Claims ### Claim 1 A package substrate for a semiconductor device, the package substrate comprising: a first substrate core; an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core and one or more second segments defined by one or more conductive vias extending through the first substrate core; a second substrate core vertically stacked with the first substrate core; and a capacitor embedded in the second substrate core in vertical alignment with the inductor embedded in the first substrate core. ### Claim 2 (depends on 1) The package substrate of claim 1, further comprising a capacitor embedded in the first substrate core. ### Claim 3 (depends on 2) The package substrate of claim 2, wherein the inductor and the capacitor embedded in the first substrate core define a voltage regulator arranged to step down a voltage output by an integrated circuit to be mounted on the package substrate. ### Claim 4 (depends on 3) The package substrate of claim 3, wherein the voltage regulator comprises a buck converter. ### Claim 5 (depends on 1) The package substrate of claim 1, wherein the inductor and the capacitor embedded in the second substrate core define a voltage regulator arranged to step down a voltage output by an integrated circuit to be mounted on the package substrate. ### Claim 6 (depends on 5) The package substrate of claim 5, wherein the voltage regulator comprises a buck converter. ### Claim 7 (depends on 1) The package substrate of claim 1, further comprising a capacitor embedded in the first substrate core, the capacitor including a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. ### Claim 8 (depends on 1) The package substrate of claim 1, wherein the capacitor includes a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. ### Claim 9 A packaged semiconductor device comprising: an integrated circuit; and a package substrate on which the integrated circuit is mounted, the package substrate comprising: a first substrate core; an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core; a second substrate core vertically stacked with the first substrate core; and a capacitor embedded in the second substrate core in vertical alignment with the inductor embedded in the first substrate core. ### Claim 10 (depends on 9) The packaged semiconductor device of claim 9, wherein the package substrate further comprises a capacitor embedded in the first substrate core. ### Claim 11 (depends on 9) The packaged semiconductor device of claim 9, wherein the inductor and the capacitor define a voltage regulator arranged to step down a voltage output by the integrated circuit. ### Claim 12 (depends on 11) The packaged semiconductor device of claim 11, wherein the voltage regulator comprises a buck converter. ### Claim 13 (depends on 9) The packaged semiconductor device of claim 9, further comprising a capacitor embedded in the first substrate core, the capacitor including a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. ### Claim 14 (depends on 9) The packaged semiconductor device of claim 9, wherein the capacitor includes a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. ### Claim 15 A package substrate for a semiconductor device, the package substrate comprising: a first substrate core; an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core, an insulating material surrounding the magnetic core, and a conductive winding surrounding the magnetic core and including one or more first segments defined by metal patterning outside the insulating material; a second substrate core vertically stacked with the first substrate core; and a capacitor embedded in the second substrate core in vertical alignment with the inductor embedded in the first substrate core. ### Claim 16 (depends on 15) The package substrate of claim 15, wherein the conductive winding further includes one or more second segments defined by conductive vias extending through the insulating material. ### Claim 17 (depends on 15) The package substrate of claim 15, wherein the inductor and the capacitor define a voltage regulator arranged to step down a voltage output by an integrated circuit to be mounted on the package substrate. ### Claim 18 (depends on 17) The package substrate of claim 17, wherein the voltage regulator comprises a buck converter. ### Claim 19 (depends on 15) The package substrate of claim 15, further comprising a capacitor embedded in the first substrate core, the capacitor including a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer. ### Claim 20 (depends on 15) The package substrate of claim 15, wherein the capacitor includes a conductive substrate having a front side and a back side, a front dielectric layer on the front side of the conductive substrate, a back dielectric layer on the back side of the conductive substrate, a front conductive polymer layer on the front dielectric layer, and a back conductive polymer layer on the back dielectric layer.