# US 12,183,690 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,690 B2 - Document ID: US12183690B2 - Status: Granted - Kind: B2 - Application number: 17/853,181 - Filed: 2022-06-29 - Published: 2022-10-20 - Granted: 2024-12-31 - Earliest claimed: 2019-12-31 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jongyoun Kim - Web page: https://patentgrep.com/patent/US12183690B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/74: {using temporarily an auxiliary support} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 40/10: Arrangements for heating - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 70/655: Fan-out layouts - H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings} - H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/014: {using batch processing} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip. ## Claims ### Claim 1 A method of manufacturing a semiconductor package, the method comprising: forming a first redistribution insulating layer; forming a lower bump pad on the first redistribution insulating layer, the lower bump pad comprising a first surface facing the first redistribution insulating layer and a second surface opposite the first surface; forming a first conductive barrier layer in contact with a side surface of the lower bump pad; forming a second redistribution insulating layer on the first redistribution insulating layer and the lower bump pad, the second redistribution insulating layer including a via opening that exposes a part of the second surface of the lower bump pad, the second redistribution insulating layer directly contacting the first conductive barrier layer; forming a redistribution pattern in the via opening of the second redistribution insulating layer, the redistribution pattern being connected to the lower bump pad; disposing a semiconductor chip on the second redistribution insulating layer; forming a first opening in the first redistribution insulating layer; and forming an external connection bump filling the first opening of the first redistribution insulating layer and in contact with the first surface of the lower bump pad, wherein the first conductive barrier layer does not extend between the lower bump pad and the external connection bump. ### Claim 2 (depends on 1) The method of claim 1, wherein the redistribution pattern comprises: a conductive via pattern extending in the via opening of the second redistribution insulating layer; and a conductive line pattern extending along a surface of the second redistribution insulating layer and connected to the conductive via pattern, and a width in a horizontal direction of the conductive via pattern increases in a direction away from the second surface of the lower bump pad. ### Claim 3 (depends on 1) The method of claim 1, wherein the external connection bump comprises a first portion filling the first opening of the first redistribution insulating layer, and a width in a horizontal direction of the first portion of the external connection bump increase in a direction away from the first surface of the lower bump pad. ### Claim 4 (depends on 1) The method of claim 1, wherein the first surface of the lower bump pad comprises: a contact portion disposed at a central portion of the lower bump pad and in direct contact with the external connection bump; and a cover portion disposed at an outer portion of the lower bump pad and not in contact with the external connection bump. ### Claim 5 (depends on 1) The method of claim 1, wherein the first conductive barrier layer extends from an upper end portion to a lower end portion of the side surface of the lower bump pad. ### Claim 6 (depends on 1) The method of claim 1, wherein the lower bump pad includes copper, and the first conductive barrier layer includes at least one of nickel and titanium. ### Claim 7 (depends on 1) The method of claim 1, further comprising, before the forming of the lower bump pad, forming a second conductive barrier layer on the first redistribution insulating layer, wherein the first surface of the lower bump pad is in contact with the second conductive barrier layer. ### Claim 8 (depends on 7) The method of claim 7, further comprising, after the forming of the first opening in the first redistribution insulating layer, removing a part of the second conductive barrier layer that is exposed through the first opening of the first redistribution insulating layer. ### Claim 9 (depends on 8) The method of claim 8, wherein the second conductive barrier layer is in contact with the external connection bump. ### Claim 10 (depends on 1) The method of claim 1, further comprising, before the forming of the lower bump pad, forming a mask pattern on the first redistribution insulating layer, the mask pattern including a mask opening, wherein, in the forming of the lower bump pad, the lower bump pad is formed in the mask opening of the mask pattern, and the mask pattern is removed after the forming of the lower bump pad. ### Claim 11 (depends on 1) The method of claim 1, further comprising, after disposing of the semiconductor chip on the second redistribution insulating layer, forming a molding layer that covers a side surface of the semiconductor chip. ### Claim 12 (depends on 11) The method of claim 11, wherein an upper surface of the molding layer is coplanar with an upper surface of the semiconductor chip. ### Claim 13 (depends on 1) The method of claim 1, wherein the lower bump pad comprises a first conductive layer, a diffusion barrier layer on the first conductive layer, and a second conductive layer on the diffusion barrier layer, and the first conductive barrier layer is in contact with a side surface of the first conductive layer, a side surface of the diffusion barrier layer, and a side surface of the second conductive layer. ### Claim 14 A method of manufacturing a semiconductor package, the method comprising: forming a redistribution structure on a carrier substrate, the redistribution structure comprising a lower bump pad including a first surface and a second surface opposite each other, a redistribution pattern in contact with the second surface of the lower bump pad, a first conductive barrier layer in contact with a side surface of the lower bump pad, a second conductive barrier layer in contact with the first surface of the lower bump pad, and a first redistribution insulating layer extending between the lower bump pad and the redistribution pattern, wherein the first redistribution insulating layer directly contacts the first conductive barrier layer, disposing a semiconductor chip on the redistribution structure; forming a molding layer on the redistribution structure, the molding layer surrounding the side surface of the semiconductor chip; separating the carrier substrate from the redistribution structure; forming a first opening in a second redistribution insulating layer, the first opening exposing a central portion of the first surface of the lower bump pad; and forming an external connection bump filling the first opening of the second redistribution insulating layer and in direct contact with the central portion of the first surface of the lower bump pad, wherein the first conductive barrier layer does not extend between the lower bump pad and the external connection bump. ### Claim 15 A method of manufacturing a semiconductor package, the method comprising: forming a first redistribution insulating layer on a carrier substrate; forming a mask pattern on the first redistribution insulating layer, the mask pattern including a mask opening; forming a lower bump pad in the mask opening of the mask pattern, the lower bump pad including a first surface facing the first redistribution insulating layer and a second surface opposite the first surface; removing the mask pattern; forming a first conductive barrier layer extending along the side surface of the lower bump pad and in contact with the side surface of the lower bump pad; forming a second redistribution insulating layer on the first redistribution insulating layer and the lower bump pad, the second redistribution insulating layer including a via opening that exposes a part of the second surface of the lower bump pad; forming a redistribution pattern that comprises a conductive via pattern and a conductive line pattern, the conductive via pattern extending in a vertical direction in the via opening of the second redistribution insulating layer, and the conductive line pattern extending along a surface of the second redistribution insulating layer and being connected to the conductive via pattern; disposing a semiconductor chip on the second redistribution insulating layer; forming a molding layer on the second redistribution insulating layer, the molding layer surrounding a side surface of the semiconductor chip; removing the carrier substrate; forming a first opening in the first redistribution insulating layer; and forming an external connection bump filling the first opening of the first redistribution insulating layer and in contact with the first surface of the lower bump pad. ### Claim 16 (depends on 15) The method of claim 15, wherein a width in a horizontal direction of the via opening of the second redistribution insulating layer increases in a direction away from the second surface of the lower bump pad, and a width in a horizontal direction of the first opening of the first redistribution insulating layer increases in a direction away from the first surface of the lower bump pad. ### Claim 17 (depends on 15) The method of claim 15, further comprising, before the forming of the lower bump pad, forming a second conductive barrier layer on the first redistribution insulating layer, wherein the lower bump pad is formed on the second conductive barrier layer, and the first surface of the lower bump pad is in contact with the second conductive barrier layer. ### Claim 18 (depends on 17) The method of claim 17, further comprising, after the forming of the first opening in the first redistribution insulating layer, removing a part of the second conductive barrier layer that is exposed through the first opening of the first redistribution insulating layer and exposing the central portion of the first surface of the lower bump pad, wherein the external connection bump is in direct contact with the central portion of the first surface of the lower bump pad. ### Claim 19 (depends on 18) The method of claim 18, wherein an outer portion of the first surface of the lower bump pad is in contact with the second conductive barrier layer, and the second conductive barrier layer is in direct contact with the external connection bump. ### Claim 20 (depends on 19) The method of claim 19, wherein a surface of the external connection bump in contact with the central portion of the first surface of the lower bump pad is coplanar with a surface of the second conductive barrier layer in contact with the outer portion of the first surface of the lower bump pad.