# US 12,183,686 B2 · Method for producing electronic component device and laminated film used therefor

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- Number: US 12,183,686 B2
- Document ID: US12183686B2
- Status: Granted
- Kind: B2
- Application number: 17/435,623
- Filed: 2020-03-05
- Published: 2022-05-19
- Granted: 2024-12-31
- Earliest claimed: 2019-03-06
- Assignees: Resonac Corporation
- Applicants: Showa Denko Materials Co., Ltd.
- Inventors: Tomoaki Shibata; Tsuyoshi Ogawa; Xinrong Li
- Web page: https://patentgrep.com/patent/US12183686B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7428: {used to support diced chips prior to mounting}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10P 72/7442: {Separation by peeling}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is a method for producing an electronic component, the method including: disposing a plurality of electronic components on an adhesive layer of a composite substrate including a support, a temporary fixing material layer, and the adhesive layer with a connection part in contact with the adhesive layer interposed between the adhesive layer and the electronic components; fixing the plurality of electronic components to the composite substrate by curing the adhesive layer; forming a sealing layer sealing the electronic components; obtaining a sealed structure by peeling off the temporary fixing material layer from the adhesive layer; and a forming a circuit surface by grinding the sealed structure from the adhesive layer side. The plurality of electronic components include an IC chip and a chip-type passive component. The passive component is disposed on the adhesive layer by a method including in the following order: disposing a conductor precursor for pattern formation as the connection part on the adhesive layer; placing the passive component on the conductor precursor; and forming a conductive pattern as the connection part by heating the conductor precursor.

## Claims

### Claim 1

A method for producing an electronic component device, the method comprising, in the following order:
preparing a composite substrate which includes a support, a temporary fixing material layer, and a curable adhesive layer laminated in this order;
disposing a plurality of electronic components on the adhesive layer of the composite substrate with a connection part in contact with the adhesive layer interposed between the adhesive layer and the electronic components;
fixing the plurality of electronic components to the composite substrate by curing the adhesive layer;
forming a sealing layer sealing the electronic components on the adhesive layer;
curing the sealing layer;
obtaining a sealed structure having the adhesive layer, the electronic components, and the sealing layer by peeling off the temporary fixing material layer from the adhesive layer; and
forming a circuit surface, the sealing layer and the connection part being exposed on the circuit surface, by grinding the sealed structure from the adhesive layer side, wherein
the plurality of electronic components include an IC chip and a chip-type passive component,
the IC chip has a main body part and a bump provided on one main surface side of the main body part,
the IC chip is disposed on the adhesive layer in a direction in which the bump as the connection part is in contact with the adhesive layer, and
the passive component is disposed on the adhesive layer by a method including in the following order: disposing a conductor precursor for pattern formation as the connection part on the adhesive layer; placing the passive component on the conductor precursor; and
forming a conductive pattern as the connection part by heating the conductor precursor.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
forming a via hole extending toward the adhesive layer from a surface of the sealing layer opposite to the adhesive layer, in the sealing layer;
filling a conductor precursor for a conductive via in the via hole; and
forming a conductive via by heating the conductor precursor in the via hole, wherein
the sealed structure further has the conductive via, and the sealed structure is ground from the adhesive layer side such that the conductive via is exposed on the circuit surface along with the sealing layer and the connection part.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the via hole is formed by an imprinting method of pushing a mold against a surface of the sealing layer opposite to the adhesive layer, before curing the sealing layer.

### Claim 4 (depends on 2)

The method according to claim 2, wherein the conductor precursor for a conductive via contains a plurality of metal particles and an organic binder in which the plurality of metal particles are dispersed, and
when the conductor precursor is heated, the plurality of metal particles form a metal sintered body through transient liquid phase sintering so as to form the conductive via including the metal sintered body.

### Claim 5 (depends on 2)

The method according to claim 2, further comprising forming a conductive shield film covering a surface of the sealing layer opposite to the connection part and connected to the conductive via.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising providing a rewiring layer having a wiring connected to the connection part on the circuit surface.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the rewiring layer is provided on the circuit surface by a method including:
preparing a rewiring structure which includes the rewiring layer having facing two main surfaces and a plurality of bumps provided on one main surface of the rewiring layer, the wiring being connected to the plurality of bumps; and
attaching the sealed structure and the rewiring structure to each other such that the connection part and at least a part of the plurality of bumps are connected to each other with an insulating adhesive layer interposed therebetween in a direction in which the circuit surface and the plurality of bumps face each other, and thereby connecting the sealed structure and the rewiring structure such that the wiring is connected to the connection part through the bump.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the rewiring structure is provided on a temporary fixing material layer of a carrier substrate including a support and the temporary fixing material layer provided on the support, and
the method further comprises peeling off the carrier substrate from the rewiring structure after providing the rewiring layer on the circuit surface.

### Claim 9 (depends on 1)

A laminated film for producing an electronic component device, the laminated film comprising: a temporary fixing material layer and a curable adhesive layer provided on the temporary fixing material layer, the laminated film being used for preparing the composite substrate in the method according to claim 1.