# US 12,183,683 B2 · Electronic package structure

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- Number: US 12,183,683 B2
- Document ID: US12183683B2
- Status: Granted
- Kind: B2
- Application number: 17/501,952
- Filed: 2021-10-14
- Published: 2023-04-20
- Granted: 2024-12-31
- Earliest claimed: 2021-10-14
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Wei-Jen Wang; Po-Jen Cheng; Fu-Yuan Chen
- Web page: https://patentgrep.com/patent/US12183683B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.

## Claims

### Claim 1

An electronic package structure comprising:
an electronic structure including an encapsulant encapsulating a semiconductor element;
a wiring structure located over the electronic structure;
an electrical contact connecting the wiring structure and the electronic structure, wherein the electrical contact includes a first side and a second side opposite to the first side; and
a support layer disposed on the encapsulant and around the electrical contact, wherein, in a cross-sectional view, the semiconductor element is exposed by an opening defined by the support layer and dividing the support layer into a first portion and a second portion spaced apart from the first portion, the first side of the electrical contact is not exposed by the first portion of the support layer, and the second side of the electrical contact is partially exposed by the support layer, wherein the support layer is further around a second electrical contact, the second electrical contact includes a first side and a second side opposite to the first side of the second electrical contact, the first side of the second electrical contact faces the first side of the electrical contact, the first side of the second electrical contact is not exposed by the second portion of the support layer.

### Claim 2 (depends on 1)

The electronic package structure of claim 1, wherein the first portion of the support layer has a first lateral surface facing a second lateral surface of the second portion of the support layer, wherein the first lateral surface includes a curved surface, and the second lateral surface includes a curved surface.

### Claim 3 (depends on 1)

The electronic package structure of claim 1, wherein, in the cross-sectional view, a lateral surface of the electrical contact includes two inflection points.

### Claim 4 (depends on 3)

The electronic package structure of claim 3, wherein an intersection between the lateral surface of the electrical contact and a top surface of the support layer is located between the two inflection points.

### Claim 5

An electronic package structure comprising:
an electronic structure including an encapsulant encapsulating a semiconductor element;
a wiring structure located over the electronic structure;
an interlayer disposed on the encapsulant; and
a gap located between the wiring structure and the electronic structure, and including a space accommodating the interlayer and a channel dividing the interlayer into a first portion and a second portion, wherein an area of the first portion of the interlayer is different from an area of the second portion of the interlayer in a top view, wherein, in the top view, the interlayer further includes a third portion separated from the first portion and the second portion, and wherein the first portion, the second portion and the third portion are disposed around the semiconductor element.

### Claim 6 (depends on 5)

The electronic package structure of claim 5, wherein, in the top view, a width of a slit between the semiconductor element and the first portion of the interlayer is non-uniform.

### Claim 7 (depends on 5)

The electronic package structure of claim 5, wherein the space is in communication with the channel, and a top surface of the semiconductor element is exposed in the channel.

### Claim 8

An electronic package structure comprising:
an electronic structure including an encapsulant encapsulating a semiconductor element and an underfill partially encapsulating the semiconductor element;
a wiring structure located over the electronic structure;
an interlayer disposed on the encapsulant; and
a gap located between the wiring structure and the electronic structure, and including a space accommodating the interlayer and a channel dividing the interlayer into a first portion and a second portion, wherein an area of the first portion of the interlayer is different from an area of the second portion of the interlayer in a top view;
wherein a top surface of the underfill is exposed in the channel.